Quaternary FET read only memory

Claim 2

A multilevel read only memory, comprising: a plurality of storage FET devices arranged into rows and columns, with each device having one predefined permanent threshold voltage out of N possible threshold voltages, N being greater than 2, with each FET in said row of FET devices having its drain connected to a common drain voltage and its source connected to a common bit line output and with each FET in said column of FET devices having its gate connected to a common word line input; whereby a binary input signal on one of said word lines generates a one-out-of N-level signal on each of said bit lines.

Claim 3

A multilevel read only memory, comprising: a plurality of storage FET devices arranged into rows and columns, with each device having one predefined threshold voltage out of N possible threshold voltages, with each FET in said row of FET devices having its drain connected to a common drain voltage and its source connected to a common bit line output and with each FET in said column of FET devices having its gate connected to a common word line input; a discharge switching FET device connected between said bit line and ground potential, having an input gate connected to a first phase clock waveform for dissipating residual electric charge on said bit line during a first phase; whereby a binary input signal on one of said word lines generates a one-out-of N-level signal on each of said bit lines.

Claim 4

A multilevel read only memory, comprising: a plurality of storage FET devices arranged into rows and columns, with each device having one predefined threshold voltage out of N possible threshold voltages, with each FET in said row of FET devices having its drain connected to a common drain voltage and its source connected to a common bit line output and with each FET in said column of FET devices having its gate connected to a common word line input; a discharge switching FET device connected between said bit line and ground potential, having an input gate connected to a first phase clock waveform for dissipating residual electric charge on said bit line during a first phase; whereby a binary input signal on one of said word lines generates a one-out-of N-level signal on each of said bit lines.

Claim 5

The multilevel read only memory of claim 2, which further comprises: a gating FET transistor connected in series with said bit line on the opposite side of said discharge FET device from said storage FET devices, having a gate connected to a second phase clock waveform following said first phase clock waveform for gating an output signal on said bit line from said storage FET devices during said second phase.

Claim 6

The multilevel read only memory of claim 1, which further comprises: said word line input selectively carrying said second phase clock waveform for turning on said storage FET devices having gates connected thereto; said bit line connected to the source of the selected storage FET device acquiring a voltage magnitude in response thereto, having a value of said gate voltage minus said predefined threshold voltage as said one-out-of N-level signal.

Claim 7

The multilevel read only memory of claim 4, which further comprises: a one-out-of N-level sense amplifier having an input connected to said bit line for amplifying the voltage magnitude of said one-out-of N-level signal.

Claim 8

The multilevel read only memory of claim 5, wherein said sense amplifier further comprises: a load device connected between said drain potential and an output node; first, second, third to (N-1) active FET devices having their drains connected to said output node, the gates connected in common to said bit line, and their sources connected to (N-1) different source potentials; said first active FET device having a threshold voltage less than said second active FET device which has a threshold voltage less than said third active FET device, which has a threshold voltage less than said (N-1) active FET device; the source potential for said first active FET device being greater than the source potential for said second FET device which is greater than the source potential for said third active FET device, which is greater than the source potential for said (N-1) active FET device; said one-out-of N-level signal input to the gates of said active FET devices undergoing an N-level inversion and amplification at said output node.

Claim 9

The multilevel read only circuit of claim 6, which further comprises: a one-out-of N-level to binary signal converter circuit having an input connected to said output node of said sense amplifier; whereby said one-out-of N-level signal amplified by said sense amplifier may be converted to a binary signal having the same numerical value as said one-out-of N-level signal.

Claim 10

The multilevel read only memory circuit of claim 7, wherein said N-level signal is a four level signal.

Claim 11

The multilevel read only circuit of claim 8, wherein said storage FET devices having their threshold adjusted during fabrication by ion-implantation of conductivity enhancing dopant ions into the channel regions thereof.

Claim 12

The multilevel read only memory circuit of claim 9, wherein said threshold voltages of said active FET devices in said sense amplifier circuit are adjusted during their fabrication by ion-implantation of conductivity enhancing dopant ions into their channel regions. .Iadd.

Claim 13

In a read-only memory wherein information storage is provided by a field-effect transistor, the improvement comprising: the transistor channel having a conductance value selected from 2 n possible values (n>1) to provide a predetermined electrical output which is characteristic of a particular set of n binary digit values, and means for decoding said electrical output into said set of n binary digit values..Iaddend. .Iadd.12. The improved read-only memory of claim 11 wherein the electrical output is characteristic of one of the possible arrangements of n bits of information, n being greater than 1..Iaddend. .Iadd.13. In a read-only memory comprising a plurality of cells wherein information storage is provided in individual cells by a field-effect transistor, the improvement wherein a cell represents one set of a plurality of sets of n bits of information, n≧2, the one set being selected from the 2 n arrangement of bits taken n at a time, comprising: the cross-sectional area of the transistor channel being selected from one of 2 n preselected values to provide an electrical output corresponding to said one set of n bits; the 2 n transistor electrical outputs forming an ordered sequence; sensing means connected to the plurality of cells and selectively activated in response to the transistor electrical outputs for producing an amplified electrical output characteristic of the one field-effect transistor output of the ordered sequence; and logic means driven by the sensing means output for generating said set of n

Claim 14

bits corresponding to the transistor output..Iaddend. .Iadd.14. The read-only memory of claim 13 wherein the electrical output is voltage and wherein the sensing means comprises 2 n -1 sense amplifiers, each having first and second input terminals and an output terminal; the first input terminal of each sense amplifier being maintained at one of a series of reference voltages intermediate the magnitude of the transistor output voltages; and the output voltage of the transistor being applied to the second input terminal for activating the sense amplifier to provide an output voltage when the second input terminal voltage exceeds the first input terminal voltage..Iaddend. .Iadd.15. A read-only memory, comprising: a matrix of memory cells, information storage being provided in individual cells thereof by a field-effect transistor, and each cell representing one set of a plurality of sets of n binary digit values, n≧2, said one set of binary digit values being selected from 2 n arrangements of bits taken n at a time; and further comprising: the cross-sectional area of the transistor channel being selected from one of 2 n preselected values to provide an electrical output representing said one set of n binary digit values; the 2 n transistor electrical outputs forming an ordered sequence; sensing means comprising 2 n -1 sense amplifiers, each sense amplifier having first and second input terminals and an output terminal; the first input terminal of each sense amplifier being maintained at one of a series of reference voltages related to the magnitude of the transistor electrical outputs; and the electrical output of the transistor being applied to the second input terminal for activating the sense amplifier when the second input terminal voltage exceeds the first input terminal voltage to provide a sense amplifier output voltage; and logic means driven by the collective output of the sense amplifiers for generating said set of n binary digit values corresponding to the

Claim 15

transistor output..Iaddend. .Iadd.16. The read-only memory of claim 15, wherein the transistor electrical output is selected from voltage and

Claim 16

current..Iaddend. .Iadd.17. A read-only memory array having a plurality of storage locations for storing digital information, comprising: at least a first storage location having a first transistor, the first transistor being capable of conducting a predetermined amount of current; and a second storage location having a second transistor, the second transistor being capable of conducting a greater amount of current than the first transistor to provide at least one storage location with capability of storing digital information which is represented by more

Claim 17

current..Iaddend. .Iadd.17. A read-only memory array having a plurality of storage locations for storing digital information, comprising: at least a first storage location having a first transistor, the first transistor being capable of conducting a predetermined amount of current; and a second storage location having a second transistor, the second transistor being capable of conducting a greater amount of current than the first transistor to provide at least one storage location with capability of storing digital information which is represented by more

Claim 18

than one digital bit..Iaddend. .Iadd.18. The memory array of claim 17 wherein the transistors are field effect transistors each having a gate electrode region..Iaddend. .Iadd.19. The memory array of claim 17 wherein the current conducting capability is controlled by the threshold voltage of the transistors..Iaddend.