Patent EP0132033A1 successfully refreshed from Google Patents.
EP0132033A1
Expired / Lapsed
EP
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Process of producing custom programmed read only memory
Assignee: American Microsystems Holding Corp
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Filing: 1984-06-04
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Granted: —
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Expires: 2004-06-04
Abstract
Abstract A late mask programming process is provided for factory programmed ROMs or logic circuitry. MOS transistors functioning as ROM cells or in logic circuitry are fabricated by a standard MOS Process. Then, a thin stop layer of silicon nitride is provided over the transistors and followed by a layer of silicon dioxide. Programming is accomplished by applying a program mask and etching through the layers overlying the gate regions of selected transistors down to the silicon nitride stop layer. The silicon nitride stop layer prevents overetching and shorting of the gates. Then, ions are implanted underneath the gates of the selected MOS transistors to alter their threshold so, for example, as ROM cells they signify a different state than those cells whose transistor gates are not implanted with ions. The silicon nitride layer serves to stop the etch solution but permits the ions to pass through, penetrate the substrate and raise the thresholds of the selected transistors. The silicon dioxide layer stops the ions from being implanted into the nonselected transistors.
Inventors
- 👤 Tarsaim L. Batra
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 17:15
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
155 words
A process of producing a custom programmed read-only memory (ROM) in a silicon wafer, the process comprising the steps of: fabricating an array of metal oxide silicon (MOS) transistors in a silicon wafer up to the stage of contact formation; depositing a layer of silicon nitride over the transistors; depositing a layer of silicon dioxide over the layer of silicon nitride; applying to the wafer a program mask containing a pattern which represents a map of selected transistors in the array of transistors of which the threshold voltages are to be altered whereby the gate regions above the selected transistors are exposed; etching the layers of silicon dioxide above the selected gate regions down to the silicon nitride layer; and implanting ions through the silicon nitride layer into the silicon regions underneath the gates to alter the threshold voltages of the selected transistors, the silicon dioxide layer serving to stop the passage of the ions.
Claim 2
Dependent Claim
155 words
A process of producing a custom programmed read-only memory (ROM) in a silicon wafer, the process comprising the steps of: fabricating an array of metal oxide silicon (MOS) transistors in a silicon wafer up to the stage of contact formation; depositing a layer of silicon nitride over the transistors; depositing a layer of silicon dioxide over the layer of silicon nitride; applying to the wafer a program mask containing a pattern which represents a map of selected transistors in the array of transistors of which the threshold voltages are to be altered whereby the gate regions above the selected transistors are exposed; etching the layers of silicon dioxide above the selected gate regions down to the silicon nitride layer; and implanting ions through the silicon nitride layer into the silicon regions underneath the gates to alter the threshold voltages of the selected transistors, the silicon dioxide layer serving to stop the passage of the ions.
Claim 3
Dependent Claim
23 words
A process as claimed in claim 1 wherein the threshold voltages of the selected transistors are lowered by the step of implanting ions.
Claim 4
Dependent Claim
23 words
A process as claimed in claim 1 wherein the threshold voltages of the selected transistors are raised by the step of implanting ions.
Claim 5
Dependent Claim
22 words
A process as claimed in claim 1, 2 or 3 wherein the array of MOS transistors is fabricated by a NMOS process.
Claim 6
Dependent Claim
22 words
A process as claimed in claim 1, 2 or 3 wherein the array of MOS transistors is fabricated by a CMOS process.
Claim 7
Dependent Claim
23 words
A process as claimed in claim 1, 2 or 3 wherein the array of MOS transistors is fabricated by a buried diffusion process.
Claim 8
Dependent Claim
21 words
A process as claimed in claim 1, 2 or 3 wherein the array of MOS transistors is by a PMOS process.
Claim 9
Dependent Claim
20 words
A process as claimed in any preceding claim wherein each selected transistor of the MOS transistors comprises a ROM cell.
Claim 10
Dependent Claim
32 words
A process as claimed in any one of claims 1 to 7 wherein at least one of the selected transistors of the array of MOS transistors is incorporated in a logic circuit.
Claim 11
Dependent Claim
27 words
A process as claimed in any preceding claim wherein the layer of silicon nitride is deposited in a thickness in the range of 100A to 1000 Å.
Claim 12
Dependent Claim
30 words
A process as claimed in any preceding claim wherein the layer of silicon dioxide is deposited in a thickness in the range of about 7,000 A to about 10,000 Å.
Claim 13
Dependent Claim
34 words
A process as claimed in any preceding claim wherein contacts to the active regions in the transistors are formed through the silicon nitride layer after the step of depositing a layer of silicon dioxide.
Claim 14
Dependent Claim
47 words
A process as claimed in any preceding claim having, after the step of implanting ions, the steps of: applying a metal mask to the wafer and forming metal interconnections between previously defined contacts to active device regions; and applying a layer of passivating material to the wafer.
Claim 15
Dependent Claim
69 words
A process as claimed in any one of claims 1 to 11 having, before the step of applying a program mask to the wafer and after the step of depositing a layer of silicon dioxide, the steps of: forming contacts to the active regions in the transistors through the silicon nitride; and applying a mask to the wafer and forming metal interconnections between the contacts to the active regions.
References Cited (Backward Citations)
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