Non-volatile semiconductor memory device

Claim 2

A non-volatile semiconductor memory device comprising a plurality of sets of series-connected memory transistors (Q mi.j ) each set being individually selectable and characterised in that in a said set each memory transistor has in parallel therewith a respective shunt selecting transistor (Q Sj.j ) controllable to by-pass the series connection of the memory transistor except when that memory transistor is to be addressed.

Claim 3

A non-volatile semiconductor memory device according to Claim 1, in which each set of series-connected memory transistors (Q mi.j ) is selectable by a selecting series transistor (Qc l ) in series therewith.

Claim 4

A non-volatile semiconductor memory device according to claim 1 or Claim 2, in which the memory (Qm i,j ) and selecting (QS i.j , Qc l ) transistors are field effect transistors.

Claim 5

A non-volatile semiconductor memory device characterized by comprising: a memory cell array formed by a plurality of memory cell array groups arranged in a matrix form of rows and columns, each of said memory cell array groups including a transistor group composed of a plurality of transistor pairs (Q M ,. j , Q Si.j ) connected in series, each transistor pair including a memory field effect transistor (Q M ,. j ) having a floating gate electrode (10) and a control gate electrode (12), and a first selecting field effect transistor (Q Si.j ) having a gate electrode (4), said memory transistor and said selecting transistor being connected in parallel with each other, and at least one second selecting field effect transistor (Q Ci ) having a gate electrode (6) and connected in series with one end of said transistor group; first word lines (Xi) each connected with the control gate electrode of said memory transistor for each row; second word lines (Zi) each connected with the gate electrode of said first selecting transistor for each row; select lines (Ci) each connected with the gate electrode of said second selecting transistor for each row; bit lines (Yi) each connected with a drain electrode of said second selecting transistor for each column; and a source line (S) commonly connected with the source electrodes of one of the transistor pairs in each of said memory cell array groups.

Claim 6

A non-volatile semiconductor memory device characterized by comprising: a memory cell array formed by a plurality of memory cell array groups arranged in a matrix form of rows and columns, each of said memory cell array groups including a transistor group composed of a plurality of transistor pairs (Q M ,. j , Q Si.j ) connected in series, each transistor pair including a memory field effect transistor (Q M ,. j ) having a floating gate electrode (10) and a control gate electrode (12), and a first selecting field effect transistor (Q Si.j ) having a gate electrode (4), said memory transistor and said selecting transistor being connected in parallel with each other, and at least one second selecting field effect transistor (Q Ci ) having a gate electrode (6) and connected in series with one end of said transistor group; first word lines (Xi) each connected with the control gate electrode of said memory transistor for each row; second word lines (Zi) each connected with the gate electrode of said first selecting transistor for each row; select lines (Ci) each connected with the gate electrode of said second selecting transistor for each row; bit lines (Yi) each connected with a drain electrode of said second selecting transistor for each column; and a source line (S) commonly connected with the source electrodes of one of the transistor pairs in each of said memory cell array groups.

Claim 7

A non-volatile semiconductor memory device according to Claims 3 or 4, in which said memory transistor (Q M ,. j ) has a channel region (8b) over-layered above the gate electrode (4) of said first or shunt selecting transistor (Q si . j ) with which it is connected in parallel and disposed on a prescribed area of a semiconductor substrate (1).

Claim 8

A non-volatile semiconductor memory device according to Claim 3 or 4, in which said memory transistors (Q M ,. j ), said first or shunt selecting transistors (Q s! . j ), and said second or series selecting transistor (Q Ci ) associated therewith are all MOS field transistors of an N-channel type.

Claim 9

A non-volatile semiconductor memory device according to any of claims 3 to 6 which further comprises polysilicon films (17) highly doped with the impurities having same conductivity type as the source/drain regions of said memory transistors, said polysilicon films being embedded between said first or shunt selecting transistors (Q Si.j ) and also between said first or shunt selecting transistor (Q Si.j ) and said second or series selecting transistor (Q Ci ).