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EP0528352A1
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Semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1992-08-12
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Granted: —
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Expires: 2012-08-12
Abstract
Abstract A refresh mode switching signal generating circuit generates a refresh mode switching signal of an H level or an L level depending on whether a particular bonding pad is wire-bonded to a power supply terminal of a package. In response to the refresh mode switching signal (RMG), the refresh mode switching circuit (RMS) switches a cycle number in a refresh mode of a semiconductor memory device, so that the cycle number in a refresh mode can be changed according to requirements of users.
Inventors
- 👤 Koichi c/o MITSUBISHI DENKI K. K. Nagase
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 14:31
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
160 words
A semiconductor memory device refreshing stored information of each memory cell in a refresh mode and including a plurality of word lines (WL), a plurality of bit line pairs (BL, /BL) arranged across these word lines, a memory cell array (MCA) including a plurality of memory cells (MC) arranged at each of crossings of said word lines and said bit line pairs, comprising: word line selecting means (RD) for selecting one of said word lines in response to row address signals (RA0-RA9); bit line pair selecting means (CD) for selecting one of said bit line pairs in response to column address signals (CA0-CA9); refresh mode switching signal generating means (RMG) for generating a refresh mode switching signal to switch types of refresh mode in response to external directions; and controlling means (RMS) for controlling the number of word lines selected simultaneously by said word line selecting means (RD) in a refresh mode in response to said refresh mode switching signal.
Claim 2
Dependent Claim
69 words
The semiconductor memory device according to claim 1, wherein said word line selecting means includes a row decoder (RD) decoding the row address signals, said row decoder being divided into a plurality of groups (RD1, RD2) whose number corresponds to a predetermined number of word lines; and wherein said controlling means (RMS) controls enabling/disabling of each group of said row decoder in response to said refresh mode switching signal.
Claim 3
Dependent Claim
76 words
The semiconductor memory device according to claim 2, wherein said row decoder is divided into two groups (RD1, RD2); and said controlling means (RMS) controls switching between a first refresh mode in which said row decoder as a whole selects the word lines one by one and a second refresh mode in which said two groups of the row decoder each select the word lines one by one in response to said refresh mode switching signal.
Claim 4
Dependent Claim
79 words
The semiconductor memory device according to claim 3, wherein said controlling means (RMS) selectively enables said two groups of the row decoder (RD1, RD2) in response to a logic level of the most significant bit (R9) of the row address signals, when said refresh mode switching signal designates said first refresh mode; and said controlling means (RMS) simultaneously enables said two groups (RD1, RD2) of the row decoder, when said refresh mode switching signal designates said second refresh mode.
Claim 5
Dependent Claim
73 words
The semiconductor memory device according to one of claims 2 to 4, further comprising: word line driving voltage generating means (WD) for generating a driving voltage for a word line selected by said row decoder, wherein said controlling means (RMS) determines which group of said row decoder should be supplied with the word line driving voltage by said word line driving voltage generating means (WD) in response to said refresh mode switching signal.
Claim 6
Dependent Claim
140 words
The semiconductor memory device according to one of claims 2 to 5, wherein said controlling means (RMS) selectively enables said two groups (RD1, RD2) of the row decoder and controls said word line driving voltage generating means (WD) such that a word line driving voltage is generated to the enabled group of the row decoder in accordance with a logic level of the most significant bit (R9) of said row address signals when said refresh mode switching signal designates said first refresh mode; and said controlling means (RMS) simultaneously enables said two groups (RD1, RD2) of the row decoder and controls said word line driving voltage generating means (WD) such that word line driving voltages are generated simultaneously to both of two groups (RD1, RD2) of the row decoder when said refresh mode switching signal designates said second refresh mode.
Claim 7
Dependent Claim
39 words
The semiconductor memory device according to one of claims 1 to 6, wherein said refresh mode switching signal generating means (RMG) generates said refresh mode switching signal in response to a voltage applied to a particular bonding pad (VBP).
Claim 8
Dependent Claim
45 words
The semiconductor memory device according to claim 7, wherein the voltage applied to said particular bonding pad (VBP) is switched depending on whether said particular bonding pad is wire-bonded or not to an particular terminal (VT) of a package (PAK) accommodating said semiconductor memory device.
Claim 9
Dependent Claim
27 words
The semiconductor memory device according to claim 8, wherein a power supply voltage or Vss (GND) is applied to said particular terminal (VT) of the package (PAK).
Claim 10
Dependent Claim
107 words
The semiconductor memory device according to one of claim 2 to 9, wherein said memory cell array (MCA) is divided into a plurality of groups (BK1, BK2) corresponding to each of the groups of said row decoder; and said each group (BK1, BK2) of the memory cell array further comprises a plurality of sense amplifiers (SA) provided for each of said bit line pairs (BL, /BL), and a plurality of transfer gates (TG3, TG4) interposed between each of said bit line pairs (BL, /BL) and each of said sense amplifiers (SA) and electrically connecting and disconnecting each of said bit lines and each of said sense amplifiers.
Claim 11
Dependent Claim
50 words
The semiconductor memory device according to claim 10, further comprising boosting means (BC) including boosting capacitances (Ca, Cb) for generating a voltage for turning on each of said transfer gates (TG3, TG4) by using these boosting capacitances; and sense amplifier activating means (SAEG) for activating each of said sense amplifiers.
Claim 12
Dependent Claim
62 words
The semiconductor memory device according to claim 11, wherein said boosting means (BC) includes means (G5, G6, TR6, TR7) for providing the generated voltage only to each of said transfer gates (TG3, TG4) included in said group of the memory cell array (BK1 and/or BK2) corresponding to said group (RD1 and/or RD2) of said row decoder enabled by said controlling means (RMS).
Claim 13
Dependent Claim
36 words
The semiconductor memory device according to claim 12 or 13, wherein said boosting means (BC) includes means (G4, TR4) for switching a capacitance value of said boosting capacitance in response to said refresh mode switching signal.
Claim 14
Dependent Claim
54 words
The semiconductor memory device according to one of claims 12 to 14, wherein said sense amplifier activating means (SAEG) activates only each of said sense amplifiers (SA) included in said group of memory cell array (BK1 and/or BK2) corresponding to said group of row decoder (RD1 and/or RD2) enabled by said controlling means (RMS).
References Cited (Backward Citations)
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