Synchronizing signal selecting circuit

Claim 2

A synchronizing signal selecting circuit comprising: (A) means for generating clock signals of a frequency larger than the frequency of said synchronizing signal; (B) a counter coupled to said means for generating clock signals for counting said clock signals during a synchronizing signal such that the count represents the duration of the synchronizing signal; (C), a reference signal generating circuit coupled to the output of said counter for generating a reference signal corresponding to the range of permissible variation in said duration in response to the count of said counter; and (D), a detecting circuit coupled to the output of said signal generating circuit for detecting said input synchronizing signal in response to the output of said reference signal generating circuit.

Claim 3

A synchronizing signal selecting circuit according to claim 1, in which said duration of said synchronizing signals corresponds to a pulse width and/or pulse period of said synchronizing signal.

Claim 4

A synchronizing signal selecting circuit according to claim 1, in which said synchronizing signal is included in a transmitted video signal.

Claim 5

A synchronizing signal selecting circuit according to claim 3, in which said synchronizing signal corresponds to a horizontal and/or a vertical synchronizing signal.

Claim 6

A synchronizing signal selecting circuit according to claim 1, in which the frequency of said clock signals is a multiple of the frequency of a color burst signal included in a transmitted video signal.

Claim 7

A synchronizing signal selecting circuit according to claim 1, in which said reference signal generating circuit is a fixed memory circuit to which the output of said counter is supplied as an address signal and from which said reference signal is obtained in accordance with the count of said counter.

Claim 8

A synchronizing signal selecting circuit according to claim 1, in which said reference signal generating circuit is a decoder circuit to decode the output of said counter into said reference signal in accordance with the count of said counter.

Claim 9

A synchronizing signal selecting circuit according to claim 1, in which said reference signal generating circuit comprises a flip-flop having a set terminal and a reset terminal, a counting output of said counter corresponding to the lowest limit of said range being coupled to said set terminal and a counting output corresponding to the highest limit of said range being supplied to said reset terminal.

Claim 10

A synchronizing signal selecting circuit according to claim 1, in which said detecting circuit comprises a flip-flop to which said reference signal is supplied and which is triggered with said synchronizing signal.

Claim 11

A synchronizing signal selecting circuit according to claim 9, in which said flip-flop is cleared at every period of said synchronizing signal, or on the basis of a carry-out signal from said counter.

Claim 12

A synchronizing signal selecting circuit comprising: (A), means for generating clock signals of a frequency larger than the pulse width and the pulse period of the synchronizing signal; (B), a first counter coupled to said means for generating clock signals for counting first clock signals corresponding to the pulse width of a synchronizing signal; (C), a first reference signal generating circuit coupled to the output of said first counter for generating a reference signal corresponding to the range of permissible variations of the pulse width of said synchronizing signal in response to the output of said first counter; (D), a first detecting circuit coupled to said first reference signal generating circuit for detecting said synchronizing signal as a proper synchronizing signal in response to the output of said reference signal generating circuit; (E), a second counter coupled to said means for generating clock signals and said first detecting circuit for counting clock signals corresponding to the pulse period; (F), a second reference signal generating circuit coupled to the output of said second counter for generating a reference signal corresponding to the range of permissible variations of the pulse period of said synchronizing signal; and (G), a second detecting circuit coupled to said second reference signal generating circuit for detecting said synchronizing signal as a proper synchronizing signal in response to the output of said second reference signal forming circuit.

Claim 13

A synchronizing signal selecting circuit comprising: (A), means for generating clock signals of a frequency larger than the pulse width and the pulse period of the synchronizing signal; (B), a first counter coupled to said means for generating clock signals for counting first clock signals corresponding to the pulse width of a synchronizing signal; (C), a first reference signal generating circuit coupled to the output of said first counter for generating a reference signal corresponding to the range of permissible variations of the pulse width of said synchronizing signal in response to the output of said first counter; (D), a first detecting circuit coupled to said first reference signal generating circuit for detecting said synchronizing signal as a proper synchronizing signal in response to the output of said reference signal generating circuit; (E), a second counter coupled to said means for generating clock signals and said first detecting circuit for counting clock signals corresponding to the pulse period; (F), a second reference signal generating circuit coupled to the output of said second counter for generating a reference signal corresponding to the range of permissible variations of the pulse period of said synchronizing signal; and (G), a second detecting circuit coupled to said second reference signal generating circuit for detecting said synchronizing signal as a proper synchronizing signal in response to the output of said second reference signal forming circuit.

Claim 14

A synchronizing signal selecting circuit according to claim 11, in which said input synchronizing signal is included in a transmitted video signal.

Claim 15

A synchronizing signal selecting circuit according to claim 12, in which said synchronizing signal corresponds to a horizontal and/or a vertical synchronizing signal.

Claim 16

A synchronizing signal generator for forming a new synchronizing signal with reference to the synchronizing signal included in transmitted video signals, comprising: (A), a frequency divider for dividing clock signals of a predetermined frequency to form said new synchronizing signal; and (B), a synchronizing signal selecting circuit for selecting proper synchronizing signals from the synchronizing signals separated from said video signals by discriminating the pulse widths and/or pulse periods of said synchronizing signals, whereby said frequency divider is reset with the output signal of said synchronizing signal selecting circuit to combine synchronously the synchronizing signal included in said video signals with the new synchronizing signal.

Claim 17

A synchronizing signal generator for forming a new synchronizing signal with reference to the synchronizing signal included in transmitted video signals, comprising: (A), a frequency divider for dividing clock signals of a predetermined frequency to form said new synchronizing signal; and (B), a synchronizing signal selecting circuit for selecting proper synchronizing signals from the synchronizing signals separated from said video signals by discriminating the pulse widths and/or pulse periods of said synchronizing signals, whereby said frequency divider is reset with the output signal of said synchronizing signal selecting circuit to combine synchronously the synchronizing signal included in said video signals with the new synchronizing signal.

Claim 18

A synchronizing signal generator according to claim 14, in which said synchronizing signal selecting circuit comprises a horizontal synchronizing signal selecting circuit for selecting proper horizontal synchronizing signals from the horizontal synchronizing signals included in said video signals, and a vertical cynchronizing signal selecting circuit for selecting proper vertical synchronizing signals from the vertical synchronizing signals included in said video signals.

Claim 19

A synchronizing signal generator according to claim 15, in which said frequency divider includes a first counter for forming a new horizontal synchronizing signal by dividing said clock signals, and a second counter for forming a new vertical synchronizing signal by dividing the frequency of said new horizontal synchronizing signal, said first counter being reset with the output signal of said horizontal synchronizing signal selecting circuit, and said second counter being reset with the output signal of said vertical synchronizing signal selecting circuit.

Claim 20

A synchronizing signal generator according to claim 14, in which said synchronizing signal selecting circuit comprises: (A), means for generating clock signals of a frequency larger than the frequency of said synchronizing signal; (B), a counter coupled to said means for generating signals for counting said clock signals during a synchronizing signal such that the count represents the pulse width and/or pulse period of a synchronizing signal; (C), a reference signal generating circuit coupled to said counter for generating a reference signal corresponding to the range of permissible variations of said one of the pulse width and/or pulse period of said synchronizing signal in response to the output of said counter; and (D), a detecting circuit coupled to said reference signal generating circuit for detecting said input synchronizing signal as a proper synchronizing signal in response to the output of said reference signal generating circuit.