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Patent US4404653A successfully refreshed from Google Patents.
US4404653A
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Associative memory cell and memory unit including same
Assignee: Yeda Research and Development Co Ltd
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Filing: 1981-10-01
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Granted: 1983-09-13
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Expires: 2001-10-01
Abstract
Abstract An associative memory cell includes a storage device having a pair of biasing nodes and a pair of output nodes, a plurality of access lines including a pair of BIT-lines and a TAG-line, and a plurality of gates controlling the accessing of the storage device by the access lines. The latter gates include a pair of sampling gates under the control of the BIT-lines and connecting the output nodes of the storage device to a pair of sampling nodes, and a pair of TAG-gates under the control of the sampling nodes and connecting the TAG-lines to one of the pair of the storage device biasing nodes. The described memory cell further includes READ-control and WRITE-control lines with the associated gates to perform the READ and WRITE functions. The pair of BIT-lines, the WRITE-control line and the READ-control line are all connected to the gate terminals of their respective gates, thereby making the device easier to drive, isolating the memory cell from the BIT-line buses, and improving reliability and speed.
Inventors
- 👤 Smil Ruhman
- 👤 Isaac Scherson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:48
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
115 words
An associative memory cell including: a storage device having a pair of biasing nodes and a pair of output nodes; a plurality of access lines accessing said storage device and including a pair of BIT-lines and a TAG-line; and a plurality of gates controlling the accessing of said storage device by said access line; characterized in that said plurality of gates include: a pair of sampling gates under the control of the BIT-lines and connecting the output nodes of the storage device to a pair of sampling nodes; and a pair of TAG-gates under the control of said sampling nodes and connecting the TAG-lines to one of the pair of the storage device biasing nodes.
Claim 2
Dependent Claim
115 words
An associative memory cell including: a storage device having a pair of biasing nodes and a pair of output nodes; a plurality of access lines accessing said storage device and including a pair of BIT-lines and a TAG-line; and a plurality of gates controlling the accessing of said storage device by said access line; characterized in that said plurality of gates include: a pair of sampling gates under the control of the BIT-lines and connecting the output nodes of the storage device to a pair of sampling nodes; and a pair of TAG-gates under the control of said sampling nodes and connecting the TAG-lines to one of the pair of the storage device biasing nodes.
Claim 3
Dependent Claim
70 words
An associative memory cell according to claim 1, wherein said memory cell further includes a READ-control line, and said plurality of gates further include a pair of READ-gates connecting one of said BIT-lines to one of said biasing nodes; one of said READ-gates being under the control of said READ-control line, the other of said READ-gates being under the control of the sampling node of the other of said BIT-lines.
Claim 4
Dependent Claim
51 words
An associative memory cell according to claim 1, wherein said memory cell further includes a WRITE-control line, and said plurality of gates further include a pair of WRITE-gates under the control of the WRITE-control line and connecting the sampling nodes to one of the pair of the storage device biasing nodes.
Claim 5
Dependent Claim
18 words
An associative memory cell according to claim 1, wherein said storage device is a static flip-flop storage device.
Claim 6
Dependent Claim
15 words
An associative memory cell according to claim 1, wherein said gates are all insulated-gate field-effect-transistors.
Claim 7
Dependent Claim
63 words
An associative memory unit including a plurality of cells each according to claim 1, said cells being disposed according to a rectangular matrix of a plurality of horizontal rows each defining a word, and a plurality of vertical columns, said BIT-lines being common to the vertical columns of cells, and said control lines and TAG-line being common to the horizontal rows of cells.
Claim 8
Dependent Claim
55 words
An associative memory unit according to claim 6, further including: a MASK-register for specifying the bits in a word to be associated; a COMPARAND-register for specifying the specific pattern to be compared; and a TAG-register for tagging the words in the memory unit which have the specified pattern in the specified bits to be associated.
Claim 9
Dependent Claim
14 words
An associative memory unit according to claim 6, incorporated in a single-chip MOS device.
Claim 10
Dependent Claim
193 words
An associative memory cell including: a storage device having a pair of biasing nodes and a pair of output nodes; a plurality of access lines accessing the storage device and including a pair of BIT-lines, a WRITE-control line, a READ-control line and a TAG-line; and a plurality of gates controlling the accessing of said storage device by said access lines; characterized in that said plurality of gates include: a pair of sampling gates under the control of the BIT-lines and connecting the output nodes of the storage device to a pair of sampling nodes; a pair of WRITE-gates under the control of the WRITE-control line and connecting the sampling nodes to the pair of storage device biasing nodes; a pair of TAG-gates under the control of said sampling nodes and connecting the TAG-line to one of the pair of storage device biasing nodes; and a pair of READ-gates connecting one of said BIT-lines to one of said storage device biasing nodes, one of said READ-gates being under the control of said READ-control line, and the other of said READ-gates being under the control of said sampling node of the other of said BIT-lines.
Claim 11
Dependent Claim
193 words
An associative memory cell including: a storage device having a pair of biasing nodes and a pair of output nodes; a plurality of access lines accessing the storage device and including a pair of BIT-lines, a WRITE-control line, a READ-control line and a TAG-line; and a plurality of gates controlling the accessing of said storage device by said access lines; characterized in that said plurality of gates include: a pair of sampling gates under the control of the BIT-lines and connecting the output nodes of the storage device to a pair of sampling nodes; a pair of WRITE-gates under the control of the WRITE-control line and connecting the sampling nodes to the pair of storage device biasing nodes; a pair of TAG-gates under the control of said sampling nodes and connecting the TAG-line to one of the pair of storage device biasing nodes; and a pair of READ-gates connecting one of said BIT-lines to one of said storage device biasing nodes, one of said READ-gates being under the control of said READ-control line, and the other of said READ-gates being under the control of said sampling node of the other of said BIT-lines.
Claim 12
Dependent Claim
29 words
An associative memory cell according to claim 9, wherein said pair of BIT-lines, WRITE-control line and READ-control line are all connected to the gate terminals of their respective gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-12 | 1987-03-14 | 1987-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-12 | 1991-03-14 | 1991-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-12 | 1995-03-14 | 1995-09-13 | $7700.00 | Window Closed / Lapsed |