Read only memory (ROM) having high density memory array with on pitch decoder circuitry

Claim 1

A Read Only Memory (ROM) comprising a substrate (A) a high density memory array including: (1) a first plurality of substantially parallel lines of a semiconductor material of one conductivity type on said substrate, (2) a second plurality of substantially parallel lines of a material different from the semiconductor material of the first lines and said second lines crossing said first lines, (3) insulating means between said first and second lines and having openings therethrough at some of the intersections of the first and second lines so that at said intersections the second line contacts the first line to form a diode; (B) a line selector including: (1) a first plurality of substantially parallel lines of the same semiconductor material as the first lines of the memory array and of a given conductivity type, said first lines being of a number equal to the number of the second lines of the memory array; (2) a second plurality of substantially parallel conductive lines which are substantially perpendicular to and cross over the first lines of the selector, insulation between said first and second selector lines at each of their intersections, and the portion of each of the first selector lines at each of said intersections being of a conductivity type opposite to that of said given conductivity type to form a MOS transistor with the second line at each of said intersections; and (3) an output line connected to at least two of said first selector lines; and (C) means electrically connecting each of the first selector lines to a separate one of the second memory array lines and along one side of the memory array, said connecting means being separate metal contacts each extending between and overlapping an end of a first selector line and an end of a second line of the memory array with said metal contacts being staggered in the direction in which the parallel lines extend in order to enable said metal contacts to overlap the ends of said lines while occupying the minimum space necessary in a direction substantially perpendicular to the direction in which said substantially parallel semiconductor lines extend.