Submicron conductor manufacturing

Claim 2

A process for manufacturing a selectable electrical resistance electrical conductor precisely positioned in electrical conduction influencing proximity to a substrate surface comprising in combination the steps of: applying a dielectric layer having a first thickness in contact with a substrate surface, applying a conductive layer having a second thickness over said dielectric layer, providing a common surface at a precise location on said substrate surface essentially perpendicular to said substrate surface of both said layers, depositing at an angle between said substrate surface direction and said essentially perpendicular common surface a conductive deposit whereby said conductive deposit exhibits a third thickness on said common surface and a fourth thickness on said substrate surface and on said conductive layer surface, and removing said conductive deposit at least to the extent of the deposit on said substrate surface.

Claim 3

The process of claim 1 wherein said removing said conductive deposit step involves removal to the depth of said fourth thickness.

Claim 4

The process of claim 1 wherein said providing step involves removal of a portion of said dielectric layer and said conductive layer along a line at a precise location on said substrate surface.

Claim 5

A self-aligned field effect transistor manufacturing process comprising in combination the steps of: applying a dielectric layer having a first thickness in contact with a substrate surface; applying a conductive layer having a second thickness over said dielectric layer; providing a common terminating surface of both said dielectric and said conductive layers at a precise location on said substrate surface essentially perpendicular to said substrate surface; depositing at an angle between said substrate surface direction and said essentially perpendicular common surface, a conductive deposit whereby said conductive deposit exhibits a third thickness on said common surface and a fourth thickness on said substrate surface and on said conductive layer surface; removing said conductive deposit at least to the extent of said fourth thickness on said substrate surface; implanting conductivity impurities into said substrate surface positioning thereby a source region and a drain region, said source region being separated from the edge of said third thickness conductive deposit and applying ohmic external contacts to each of said source and drain regions.

Claim 6

A self-aligned field effect transistor manufacturing process comprising in combination the steps of: applying a dielectric layer having a first thickness in contact with a substrate surface; applying a conductive layer having a second thickness over said dielectric layer; providing a common terminating surface of both said dielectric and said conductive layers at a precise location on said substrate surface essentially perpendicular to said substrate surface; depositing at an angle between said substrate surface direction and said essentially perpendicular common surface, a conductive deposit whereby said conductive deposit exhibits a third thickness on said common surface and a fourth thickness on said substrate surface and on said conductive layer surface; removing said conductive deposit at least to the extent of said fourth thickness on said substrate surface; implanting conductivity impurities into said substrate surface positioning thereby a source region and a drain region, said source region being separated from the edge of said third thickness conductive deposit and applying ohmic external contacts to each of said source and drain regions.

Claim 7

The transistor manufacturing process of claim 4 wherein said implantation step is performed at an angle.

Claim 8

In a process of forming a low resistivity submicron electrode with an external connection along the length thereof on a substrate by angular deposition against a positioned surface essentially perpendicular to said substrate whereby there is provided a heavier mass of conductor perpendicular to the surface of said substrate than parallel to said substrate surface and the use of the difference between the horizontal and vertical to produce an edge defined vertical conductor structure, the improvement for external electrical connection purposes comprising the fabrication of said positioned surface against which said angular deposition is to take place of a first insulating layer adjacent the substrate surface covered by a second external electrical connection layer coterminating at said positioned surface.

Claim 9

In a process of forming a low resistivity submicron electrode with an external connection along the length thereof on a substrate by angular deposition against a positioned surface essentially perpendicular to said substrate whereby there is provided a heavier mass of conductor perpendicular to the surface of said substrate than parallel to said substrate surface and the use of the difference between the horizontal and vertical to produce an edge defined vertical conductor structure, the improvement for external electrical connection purposes comprising the fabrication of said positioned surface against which said angular deposition is to take place of a first insulating layer adjacent the substrate surface covered by a second external electrical connection layer coterminating at said positioned surface.