Apparatus for driving liquid crystal display

Claim 2

A circuit for accepting from a data source video information which is intended for a cathode-ray-tube (CRT) screen and providing video signals for display onto a liquid crystal display (LDC) screen comprising: a data line coupled to said data source for transferring of said video information to said circuit; a memory coupled to said data line for storing said video information; addressing means coupled to said memory for addressing locations of said memory; first counting means coupled to said addressing means for providing address signals to input said video information into said memory; second counting means, operating independent of said first counting means, coupled to said addressing means for providing address signals to output said video information from said memory; output means coupled to said memory and said LCD screen for receiving an output of said memory and generating said video signals to said LCD screen; controlling means coupled to said memory, output means, address means, first and second counting means for generating control and timing signals which provide for said video information to be divided into a plurality of segments as it is loaded into said memory and outputting said segments, such that said video information ,when input into said memory, is subsequently generated as a plurality of segments; said output means receiving said plurality of segments for said video information and providing said segments for substantially simultaneous presentation on said LCD screen; whereby said video information intended for said CRT screen is displayed on said LCD screen.

Claim 3

The circuit as defined by claim 2 wherein said memory includes a plurality of random access memories (RAMs).

Claim 4

The circuit as defined by claim 2 wherein said addressing means includes a multiplexer to switch between outputs of first and second counting means.

Claim 5

The circuit as defined by claim 3 wherein said output means includes a plurality of shift registers for converting said output of said memory to a plurality of segmented serial video signals.

Claim 6

The circuit as defined by claim 4 wherein said first counting means includes a plurality of binary counters.

Claim 7

The circuit as defined by claim 5 wherein said second counting means includes a plurality of binary counters.

Claim 8

A circuit for accepting from a data source serial video information which is intended for a cathode-ray-tube (CRT) screen and providing video signals for display onto a liquid crystal display (LCD) screen comprising: input means coupled to said data course for receiving a stream of serial video information from said data source and converting said serial video information to parallel data; a memory for storing said video information, said memory coupled to said input means; output means coupled to said memory and said LCD screen; addressing means coupled to said memory for addressing locations of said memory; a first counter coupled to said addressing means for providing address signals to input said parallel data into said memory; a second counter, operating independent of said first counter, coupled to said addressing means for providing address signals to output said video information from said memory; controlling means coupled to said memory, input means, output means, addressing means, first and second counters for generating control and timing signals which provide for said video information to be converted to parallel data and divided into a plurality of segments as it is loaded into said memory by locations addressed by said first counter; said control means subsequently accessing said memory by locations addressed by said second counter, wherein said memory outputs said plurality of segments to said output means; said output means receiving said plurality of segments for said video information and providing said segments for substantially simultaneous presentation of said LCD screen; whereby said video information intended for said CRT screen is displayed on said LCD screen.

Claim 9

A circuit for accepting from a data source serial video information which is intended for a cathode-ray-tube (CRT) screen and providing video signals for display onto a liquid crystal display (LCD) screen comprising: input means coupled to said data course for receiving a stream of serial video information from said data source and converting said serial video information to parallel data; a memory for storing said video information, said memory coupled to said input means; output means coupled to said memory and said LCD screen; addressing means coupled to said memory for addressing locations of said memory; a first counter coupled to said addressing means for providing address signals to input said parallel data into said memory; a second counter, operating independent of said first counter, coupled to said addressing means for providing address signals to output said video information from said memory; controlling means coupled to said memory, input means, output means, addressing means, first and second counters for generating control and timing signals which provide for said video information to be converted to parallel data and divided into a plurality of segments as it is loaded into said memory by locations addressed by said first counter; said control means subsequently accessing said memory by locations addressed by said second counter, wherein said memory outputs said plurality of segments to said output means; said output means receiving said plurality of segments for said video information and providing said segments for substantially simultaneous presentation of said LCD screen; whereby said video information intended for said CRT screen is displayed on said LCD screen.

Claim 10

The circuit as defined by claim 7 wherein said addressing means includes a mutliplexer to switch between outputs of first and second counters.

Claim 11

The circuit as defined by claim 8 wherein said memory includes two Random Access Memories (RAMs), the first of said RAMS storing information corresponding to a first segment and the second of said RAMs storing information corresponding to a remaining segment.

Claim 12

The circuit as defined by claim 9 wherein said output means includes shift registers, each of said registers coupled to receive a segmented output from said RAMs and converting each segment to a serial data stream for substantially simultaneously presentation of said segments comprising said video information to said LCD screen.

Claim 13

The circuit as defined by claim 10 wherein said first and second counters operate independently of each other and at approximately the same rate of speed.

Claim 14

The circuit as defined by claim 11 wherein said first counter includes a plurality of binary counters.

Claim 15

The circuit as defined by claim 12 wherein the second counter includes a plurality of binary counters.

Claim 16

The circuit as defined by claim 11 wherein said LCD screen is approximately rectangular and is electrically divided into four rectangular equal-sized quadrants corresponding to the upper left, upper right, lower left and lower right portions of said screen, such that each said segment corresponds to one of said quadrants.

Claim 17

The circuit as defined by claim 11 wherein said LCD screen is approximately rectangular and is electrically divided into a top half and a bottom half, such that each said segment corresponds to one of said halves.