Semiconductor memory device

Claim 2

A semiconductor memory device comprising: dynamic memory cell which includes a series connection comprising a switching MISFET and a storage capacitor connected in series, said storage capacitor comprising a first electrode, a silicon nitride film formed over said first electrode, and a second electrode formed over said silicon nitride film; a bit line which is connected to one of said series connection and which supplies a signal voltage having a predetermined maximum value to said dynamic memory cell; and a terminal which is connected to the other end of said series connection and which supplies a voltage to said other end of said series connection so that a voltage of said storage capacitor to be stored between said first electrode and said second electrode has a smaller absolute value than an absolute value of said maximum value of said signal voltage supplied to said bit line.

Claim 3

A semiconductor memory device according to claim 1, wherein a voltage substantially equal to half of said maximum signal voltage is applied to said terminal.

Claim 4

A semiconductor memory device according to claim 2, wherein said first electrode of said storage capacitor comprises a semiconductor layer.

Claim 5

A semiconductor memory device according to claim 3, wherein said semiconductor layer includes a polycrystalline silicon layer.

Claim 6

A semiconductor memory device according to claim 1, further comprising a silicon oxide film formed between said first electrode and said silicon nitride film.

Claim 7

A semiconductor memory device according to claim 1, further comprising a silicon oxide film formed between said second electrode and said silicon nitride film.

Claim 8

A semiconductor memory device according to claim 4, further comprising a first silicon oxide film formed between said first electrode and said silicon nitride film, and a second silicon oxide film formed between said second electrode and said silicon nitride film.

Claim 9

A semiconductor memory device comprising: a dynamic memory cell which includes a series connection comprising a switching MISFET and a storage capacitor connected in series, said storage capacitor comprising a first electrode, a silicon nitride film formed over said first electrode, and a second electrode formed over said silicon nitride film; a bit line which is connected to one end of said series connection and which supplies a signal voltage having a predetermined high level Vh and a predetermined low level Vl to said dynamic memory cell; and a terminal which is connected to the other end of said series connection and which supplies a voltage Vp which is greater than said low level Vl but less than said high level Vh to said other end of said series connection so that a voltage Vs of said storage capacitor to be stored between said first electrode and said second electrode has a smaller absolute value than the absolute value of said high level Vh of said signal voltage.

Claim 10

A semiconductor memory device comprising: a dynamic memory cell which includes a series connection comprising a switching MISFET and a storage capacitor connected in series, said storage capacitor comprising a first electrode, a silicon nitride film formed over said first electrode, and a second electrode formed over said silicon nitride film; a bit line which is connected to one end of said series connection and which supplies a signal voltage having a predetermined high level Vh and a predetermined low level Vl to said dynamic memory cell; and a terminal which is connected to the other end of said series connection and which supplies a voltage Vp which is greater than said low level Vl but less than said high level Vh to said other end of said series connection so that a voltage Vs of said storage capacitor to be stored between said first electrode and said second electrode has a smaller absolute value than the absolute value of said high level Vh of said signal voltage.

Claim 11

A semiconductor memory device according to claim 8, wherein Vp=(Vh+Vl)/2.

Claim 12

A semiconductor memory device according to claim 9, wherein said first electrode of said storage capacitor comprises a polycrystalline silicon layer.

Claim 13

A semiconductor memory device according to claim 8, further comprising a silicon oxide film formed between said first electrode and said silicon nitride film.

Claim 14

A semiconductor memory device according to claim 8, further comprising a silicon oxide film formed between said second electrode and said silicon nitride film.

Claim 15

A semiconductor memory device comprising: a dynamic memory cell which includes a series connection comprising a switching MISFET and a storage capacitor connected in series, said storage capacitor comprising a first electrode, a silicon nitride film, and a second electrode; a bit line which is connected to one end of said series connection; amplifier means which is coupled to said bit line and which applies a signal having one level of a predetermined high level and a predetermined low level to said bit line; and a terminal which is connected to the other end of said series connection and which supplies a voltage which is greater than said low level but less than said high level to said other end of said series connection so that a voltage of said storage capacitor to be stored between said first electrode and said second electrode has a smaller absolute value than the absolute value of said high level of said signal.

Claim 16

A semiconductor memory device comprising: a dynamic memory cell which includes a series connection comprising a switching MISFET and a storage capacitor connected in series, said storage capacitor comprising a first electrode, a silicon nitride film, and a second electrode; a bit line which is connected to one end of said series connection; amplifier means which is coupled to said bit line and which applies a signal having one level of a predetermined high level and a predetermined low level to said bit line; and a terminal which is connected to the other end of said series connection and which supplies a voltage which is greater than said low level but less than said high level to said other end of said series connection so that a voltage of said storage capacitor to be stored between said first electrode and said second electrode has a smaller absolute value than the absolute value of said high level of said signal.

Claim 17

A semiconductor memory device according to claim 13, wherein said MISFET has a region connected to said second electrode of said storage capacitor and a region connected to said bit line, and wherein said first electrode of said storage capacitor is connected to said terminal.

Claim 18

A semiconductor memory device according to claim 14, wherein said first electrode is formed over said silicon nitride film and said silicon nitride film is formed over said second electrode.

Claim 19

A semiconductor memory device according to claim 15, wherein said amplifier means includes means for generating said signal having either said predetermined high level or said predetermined low level in accordance with data stored in said dynamic memory cell.

Claim 20

A semiconductor memory device according to claim 16, further comprising a silicon oxide film formed between said first electrode and said silicon nitride film.

Claim 21

A semiconductor memory device according to claim 17, further comprising a silicon oxide film formed between said second electrode and said silicon nitride film.

Claim 22

A semiconductor memory device according to claim 16, further comprising a silicon oxide film formed between said second electrode and said silicon nitride film.

Claim 23

A semiconductor memory device according to claim 13, wherein said first electrode is formed over said silicon nitride film and said silicon nitride film is formed over said second electrode.

Claim 24

A semiconductor memory device according to claim 20, further comprising a silicon oxide film formed between said first electrode and said silicon nitride film.

Claim 25

A semiconductor memory device according to claim 20, further comprising a silicon oxide film formed between said second electrode and said silicon nitride film.