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US4784968A
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Process for manufacturing a semiconductor device having MIS-type field effect transistors with impurity region below the gate electrode
Assignee: Hitachi Ltd
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Filing: 1987-07-20
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Granted: 1988-11-15
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Expires: 2007-07-20
Abstract
Abstract Disclosed herein is a MOS-type field-effect transistor in which a semiconductor region having the same type of conductivity as the substrate and an impurity concentration higher than that of the substrate is formed under the channel so as to come at both ends thereof into contact with the source and drain regions. The semiconductor region restricts the extension of depletion layer from the source and drain regions, and restricts the short-channel effect. The junction capacity is small between the semiconductor region and the source and drain regions.
Inventors
- 👤 Kazuhiro Komori
- 👤 Kenichi Kuroda
- 👤 Kousuke Okuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:18
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/351; H10D62/357; H10D62/364; H10D62/371; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/919
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
220 words
A process for producing a semiconductor device having a MIS-type field-effect transistor formed in a first semiconductor region of a first type of conductivity in a semiconductor substrate, comprising the steps of: forming a second semiconductor region in said first semiconductor region, said second semiconductor region being separated from the surface of said semiconductor substrate, and said second semiconductor region further having the same type of conductivity as said first semiconductor region and an impurity concentration higher than that of said first semiconductor region; forming a gate electrode on a gate insulating film on said semiconductor substrate, after said second semiconductor region has been formed; introducing impurities of a second type of conductivity into said first semiconductor region using at least said gate electrode as a mask, so as to provide a first introduction step, said first introduction step being effected by the implantation of ions, so that the impurity concentration of the first type of conductivity is substantially lowered in said second semiconductor region except a portion at least under said gate electrode; and introducing impurities of the second type of conductivity into said first semiconductor region using at least said gate electrode as a mask, so as to provide a second introduction step, said second introduction step forming at least a part of the source and drain regions.
Claim 2
Dependent Claim
220 words
A process for producing a semiconductor device having a MIS-type field-effect transistor formed in a first semiconductor region of a first type of conductivity in a semiconductor substrate, comprising the steps of: forming a second semiconductor region in said first semiconductor region, said second semiconductor region being separated from the surface of said semiconductor substrate, and said second semiconductor region further having the same type of conductivity as said first semiconductor region and an impurity concentration higher than that of said first semiconductor region; forming a gate electrode on a gate insulating film on said semiconductor substrate, after said second semiconductor region has been formed; introducing impurities of a second type of conductivity into said first semiconductor region using at least said gate electrode as a mask, so as to provide a first introduction step, said first introduction step being effected by the implantation of ions, so that the impurity concentration of the first type of conductivity is substantially lowered in said second semiconductor region except a portion at least under said gate electrode; and introducing impurities of the second type of conductivity into said first semiconductor region using at least said gate electrode as a mask, so as to provide a second introduction step, said second introduction step forming at least a part of the source and drain regions.
Claim 3
Dependent Claim
27 words
A process for producing a semiconductor device according to claim 1, wherein said gate electrode is used as a mask in said first and second introduction steps.
Claim 4
Dependent Claim
100 words
A process for producing a semiconductor device according to claim 1, wherein said first introduction step uses said gate electrode as a mask, and wherein said second introduction step includes introducing impurities of the second type of conductivity into the substrate twice, in a third introduction step and in a fourth introduction step which introduces impurities at a concentration higher than that of said third introduction step, said third introduction step using said gate electrode as a mask, and said fourth introduction step using said gate electrode and spacers formed on both sides of said gate electrode as a mask.
Claim 5
Dependent Claim
99 words
A process for producing a semiconductor device according to claim 1, wherein said first introduction step uses said gate electrode and spacers formed on both sides of said gate electrode as masks, and wherein said second introduction step includes introducing impurities of the second conductivity type into the substrate twice, in a third introduction step and a fourth introduction step which introduces impurities at a concentration higher than that of said third introduction step, said third introduction step using said gate electrode as a mask, and said fourth introduction step using said gate electrode and said spacers as masks.
Claim 6
Dependent Claim
32 words
A process for producing a semiconductor device according to claim 1, further comprising a step for forming, on said gate electrode, a film which has the shape same as said gate electrode.
Claim 7
Dependent Claim
39 words
A process for producing a semiconductor device according to claim 1, further comprising a step for forming a semiconductor region of the second type of conductivity in a portion shallower than said second semiconductor region under said gate electrode.
Claim 8
Dependent Claim
42 words
A process for producing a semiconductor device according to claim 1, wherein in the first introduction step the impurities of the second conductivity type compensate the impurities of the first type of conductivity except said portion at least under said gate electrode.
Claim 9
Dependent Claim
33 words
A process for producing a semiconductor device according to claim 1, wherein the impurity concentration of impurities introduced in the first introduction step is not higher than that of the second semiconductor region.
Claim 10
Dependent Claim
41 words
A process for producing a semiconductor device according to claim 2, wherein said second introduction step is carried out after said first introduction step has been carried out, and said source and drain regions are formed by said second introduction step.
Claim 11
Dependent Claim
42 words
A process for producing a semiconductor device according to claim 3, wherein said third introduction step is carried out after said first introduction step has been carried out, and said spacers are formed after said third introduction step has been carried out.
Claim 12
Dependent Claim
42 words
A process for producing a semiconductor device according to claim 4, wherein said spacers are formed after said third introduction step has been carried out, and said fourth introduction step is carried out after said first introduction step has been carried out.
Claim 13
Dependent Claim
57 words
A process for producing a semiconductor device according to claim 4, wherein said spacers are formed after said third introduction step has been carried out, said first and fourth introduction steps are carried out simultaneously, and the semiconductor region formed by said fourth introduction step is deeper than the semiconductor region formed by said third introduction step.
Claim 14
Dependent Claim
28 words
A process for producing a semiconductor device according to claim 4, wherein said semiconductor region formed by the fourth introduction step is deeper than the second semiconductor region.
Claim 15
Dependent Claim
32 words
A process for producing a semiconductor device according to claim 8, wherein the impurity concentration of impurities introduced in the first introduction step is greater than that of the first semiconductor region.
Claim 16
Dependent Claim
33 words
A process for producing a semiconductor device according to claim 10, wherein a semiconductor region formed by said fourth introduction step is deeper than a semiconductor region formed by said third introduction step.
Claim 17
Dependent Claim
33 words
A process for producing a semiconductor device according to claim 11, wherein the semiconductor region formed by said fourth introduction step is deeper than the semiconductor region formed by said third introduction step.
Claim 18
Dependent Claim
28 words
A process for producing a semiconductor device according to claim 16, wherein said semiconductor region formed by the fourth introduction step is deeper than the second semiconductor region.
Claim 19
Dependent Claim
200 words
A process for producing a semiconductor device having a MIS-type field-effect transistor formed in a first semiconductor region of a first type of conductivity in a semiconductor substrate, comprising the steps of: forming a gate electrode on a gate insulating film on said semiconductor substrate; forming a second semiconductor region by implanting ions in said first semiconductor region after said gate electrode has been formed, said second semiconductor region being shallower under said gate electrode than other portions, and said second semiconductor region further having the same type of conductivity as said first semiconductor region and an impurity concentration higher than that of said first semiconductor region; implanting impurity ions of a second type of conductivity into said first semiconductor region, so as to provide a first introduction step, so that the impurity concentration of the first type of conductivity is substantially lowered in said second semiconductor region except a portion at least under said gate electrode; and introducing impurities of the second type of conductivity into said first semiconductor region using at least said gate electrode as a mask, so as to provide a second introduction step, to form at least a part of the source and drain regions.
Claim 20
Dependent Claim
200 words
A process for producing a semiconductor device having a MIS-type field-effect transistor formed in a first semiconductor region of a first type of conductivity in a semiconductor substrate, comprising the steps of: forming a gate electrode on a gate insulating film on said semiconductor substrate; forming a second semiconductor region by implanting ions in said first semiconductor region after said gate electrode has been formed, said second semiconductor region being shallower under said gate electrode than other portions, and said second semiconductor region further having the same type of conductivity as said first semiconductor region and an impurity concentration higher than that of said first semiconductor region; implanting impurity ions of a second type of conductivity into said first semiconductor region, so as to provide a first introduction step, so that the impurity concentration of the first type of conductivity is substantially lowered in said second semiconductor region except a portion at least under said gate electrode; and introducing impurities of the second type of conductivity into said first semiconductor region using at least said gate electrode as a mask, so as to provide a second introduction step, to form at least a part of the source and drain regions.
Claim 21
Dependent Claim
55 words
A process for producing a semiconductor device according to claim 18, wherein said first introduction step introduces impurity ions of the second type of conductivity beneath the gate electrode so as to compensate impurities for forming the second semiconductor region, whereby the second semiconductor region is formed separated from the surface of the semiconductor substrate.
Claim 22
Dependent Claim
42 words
A process for producing a semiconductor device according to claim 19, wherein in the first introduction step the impurities of the second conductivity type compensate the impurities of the first type of conductivity except said portion at least under said gate electrode.
Claim 23
Dependent Claim
129 words
A process for producing a semiconductor device according to claim 19, wherein the first introduction step is performed so as to compensate for the impurity concentration of the first type of conductivity except for at least a portion under the gate electrode, separated from the surface of the semiconductor substrate, and a portion beneath where the source and drain regions are to be formed, the portion beneath where the source and drain regions are to be formed being deeper than the portion under the gate electrode; and wherein in the second introduction step the impurities are introduced so as to form the at least a part of the source and drain regions spaced from and above said portion beneath where the source and drain regions are to be formed.
Claim 24
Dependent Claim
87 words
A process for producing a semiconductor device according to claim 19, wherein said second introduction step includes introducing impurities of the second type of conductivity into the substrate twice, in a third introduction step and in a fourth introduction step which introduces impurities at a concentration higher than that of said third introduction step, said third introduction step using said gate electrode as a mask, and said fourth introduction step using said gate electrode and spacers formed on both sides of said gate electrode as a mask.
Claim 25
Dependent Claim
48 words
A process for producing a semiconductor device according to claim 22, wherein said third introduction step is performed such that the regions formed introducing impurities in the third introduction step come into contact with both sides of a portion of the second semiconductor region beneath the gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |