Gate array integrated circuit device and method thereof for providing various bit/word constructions

Claim 1

A gate array integrated circuit device comprising: a basic cell array region in which a plurality of basic cells are arranged; a rectangular memory cell matrix region in which a plurality of memory cells are arranged, said memory cell matrix region having first and second sides, the first side being opposite the second side, and having a third side; and a plurality of peripheral circuits each of which includes address input circuits and decoders for accessing said memory cells, including: first and second peripheral circuits arranged along the first and second sides of said rectangular memory cell matrix region, said peripheral circuits connected to at least tow independent memories, and each including: a clock buffer; a word decoder; and an address register; and a third peripheral circuit arranged along said third side of said rectangular memory cell matrix region and including: a column selector; and a sense amplifier.

Claim 5

A method for producing a semiconductor device comprising the steps of: (a) forming, in advance, a semiconductor chip provided with a basic cell array region in which a plurality of basic cells are arranged, a rectangular memory cell matrix region in which a plurality of memory cells are arranged, and a plurality of peripheral circuits, formed along first and second sides of the periphery of the rectangular memory cell matrix, each of which includes address input circuits and decoders for accessing the memory cells; (b) connecting the basic cells to each other to form a predetermined logic circuit; (c) forming word lines in a first direction of the rectangular memory cell matrix region and forming bit lines in a second direction of the memory cell matrix region, the first direction being perpendicular to the second direction, according to a predetermined bit/word construction; (d) forming at least one of first and second groups of word lines and bit lines; and (e) connecting one of the groups of word lines and bit lines to each of the plurality of peripheral circuits, thereby forming at least two independent memories.

Claim 6

A method for producing a semiconductor device comprising the steps of: (a) forming, in advance, a semiconductor chip provided with a basic cell array region in which a plurality of basic cells are arranged, a rectangular memory cell matrix region in which a plurality of memory cells are arranged, and a plurality of peripheral circuits, formed along first and second sides of the periphery of the rectangular memory cell matrix, each of which includes address input circuits and decoders for accessing the memory cells; (b) connecting the basic cells to each other to form a predetermined logic circuit; (c) forming word lines in a first direction of the rectangular memory cell matrix region and forming bit lines in a second direction of the memory cell matrix region, the first direction being perpendicular to the second direction, according to a predetermined bit/word construction; (d) forming at least one of first and second groups of word lines and bit lines; and (e) connecting one of the groups of word lines and bit lines to each of the plurality of peripheral circuits, thereby forming at least two independent memories.

Claim 9

A method for producing a semiconductor device, comprising the steps of: (a) forming a semiconductor chip including a basic cell array region having basic cells, a rectangular memory cell matrix formed adjacent to the basic cell array region, and peripheral circuits formed along first and second sides of the periphery of the rectangular memory cell matrix; (b) connecting the basic cells for forming a predetermined logic circuit; (c) forming one of a group of word lines and bit lines in the rectangular memory cell matrix in accordance with a desired bit/word construction, the one of the group of word lines and bit lines being divided into at least two independent groups of word lines and bit lines; and (d) connecting the at least two independent groups of words lines and bit lines to at least two opposed peripheral circuits to form at least two independent memories.

Claim 10

A method for producing a semiconductor device, comprising the steps of: (a) forming a semiconductor chip including a basic cell array region having basic cells, a rectangular memory cell matrix formed adjacent to the basic cell array region, and peripheral circuits formed along first and second sides of the periphery of the rectangular memory cell matrix; (b) connecting the basic cells for forming a predetermined logic circuit; (c) forming one of a group of word lines and bit lines in the rectangular memory cell matrix in accordance with a desired bit/word construction, the one of the group of word lines and bit lines being divided into at least two independent groups of word lines and bit lines; and (d) connecting the at least two independent groups of words lines and bit lines to at least two opposed peripheral circuits to form at least two independent memories.