US4804641A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for limiting chippage when sawing a semiconductor wafer
Assignee: Siemens AG
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Filing: 1986-09-11
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Granted: 1989-02-14
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Expires: 2006-09-11
Abstract
Abstract A method for limiting chippage when sawing a semiconductor wafer into individual pieces which involves providing a dielectric layer at least in some portions of the wafer surface. A border of the dielectric layer is applied to the margins of the individual parts which are to be formed on the surface of the semiconductor wafer, being applied under such conditions that the margins exert a tensile stress on the semiconductor surface. This produces a symmetrical tensile stress distribution for limiting the chippage of the semiconductor material in the sawing region on the surface of the semiconductor wafer.
Inventors
- 👤 Manfred Arlt
- 👤 Joachim Dathe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:00
CPC Classifications
H; H10; H10P; H10P52/00; Y; Y10; Y10S; Y10S148/00; Y10S148/028
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
99 words
A method for preparing a semiconductor wafer for sawing to limit chippage upon sawing it into individual pieces which comprises: applying a dielectric layer in limited portions of said wafer in the form of a border spaced from margins of those portions which are to form individual parts, and spaced from the sawing line to be employed, said dielectric layer being applied under conditions such that said border is under compressive stress and exerts a tensile stress on the semiconductor surface said border providing a symmetrical tensile stress distribution for limiting the chippage of the semiconductor material during sawing.
Claim 2
Independent Claim
99 words
A method for preparing a semiconductor wafer for sawing to limit chippage upon sawing it into individual pieces which comprises: applying a dielectric layer in limited portions of said wafer in the form of a border spaced from margins of those portions which are to form individual parts, and spaced from the sawing line to be employed, said dielectric layer being applied under conditions such that said border is under compressive stress and exerts a tensile stress on the semiconductor surface said border providing a symmetrical tensile stress distribution for limiting the chippage of the semiconductor material during sawing.
Claim 3
Dependent Claim
25 words
A method according to claim 1 in which said dielectric layer is applied by thermal oxidation of the wafer surface to produce a dielectric oxide.
Claim 4
Dependent Claim
21 words
A method according to claim 1 wherein said dielectric layer is applied by depositing an oxide layer on said wafer surface.
Claim 5
Dependent Claim
21 words
A method according to claim 1 wherein said dielectric layer is applied by depositing a nitride layer on said wafer surface.
Claim 6
Dependent Claim
16 words
A method according to claim 1 wherein said dielectric layer is applied at an elevated temperature.
Claim 7
Dependent Claim
19 words
A method according to claim 1 wherein said semiconductor wafer is suddenly cooled during application of said dielectric layer.
Claim 8
Independent Claim
26 words
A method according to claim.1 wherein said border has a width on the order of 1 micron and a thickness on the order of 0.1 micron.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-14 | 1992-08-15 | 1993-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-14 | 1996-08-15 | 1997-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-14 | 2000-08-15 | 2001-02-14 | $7700.00 | Window Closed / Lapsed |