Patent US4811293A successfully refreshed from Google Patents.
US4811293A
Expired / Lapsed
US
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Method for storing data in an electrically erasable memory for carrying out this method
Assignee: Sartorius AG
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Filing: 1986-04-15
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Granted: 1989-03-07
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Expires: 2006-04-15
Abstract
Abstract Method and apparatus of storing data in an electrically erasable memory connected to a microprocessor to effectively protect data stored in the memory from being unintentionally overwritten in cases of defective operation of the microprocessor, an overwrite protection system consisting of a write protect flip-flop (1) whose two logical states signify "with write protection" and "without write protction" and also a gate (3) in the write line which is controlled by the write protect flip-flop and in whose logical "with write protection" state, write errors are prevented from being conducted to the individual memory locations, and, finally a mechanical switch element (5) whereby these components are connected in such a manner that the write protect flip-flop (1) can only be brought into the one logical "with write protection" state by the microprocessor, while it can only be brought into the other logical "without write protection" state, if and when the mechanical switch element (5) is actuated. The overwrite protection can apply depending on the embodiment to the entire electronically erasable memory or only to the subareas thereof.
Inventors
- 👤 Erich Knothe
- 👤 Franz-Josef Melcher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:15
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/22; G11C7/00; G11C7/24
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
118 words
Method of storing data in an electrically erasable memory connected to a microprocessor, comprising the steps of inputing any data from the microprocessor into the electrically erasable memory during an initialization phase, defining at least a subarea of the electrically erasable memory as write-protected at the end of the initialization phase by setting at least one write protect flip-flop means, blocking a write line to the associated subarea of the electrically erasable memory in its logical "with write protection" state, and bringing the write protect flip-flop means into the logical "with write protect" state by the microprocessor, while it can only be brought into the other logical "without write protect" state by actuation of a mechanical switch means.
Claim 2
Dependent Claim
118 words
Method of storing data in an electrically erasable memory connected to a microprocessor, comprising the steps of inputing any data from the microprocessor into the electrically erasable memory during an initialization phase, defining at least a subarea of the electrically erasable memory as write-protected at the end of the initialization phase by setting at least one write protect flip-flop means, blocking a write line to the associated subarea of the electrically erasable memory in its logical "with write protection" state, and bringing the write protect flip-flop means into the logical "with write protect" state by the microprocessor, while it can only be brought into the other logical "without write protect" state by actuation of a mechanical switch means.
Claim 3
Dependent Claim
37 words
Method according to claim 1, characterized in that the write protect flip-flop means can be brought into the logical "without write protection" state only by actuating the mechanical switch means and, additionally, by a selected microprocessor command.
Claim 4
Dependent Claim
35 words
Method according to claim 1 or 2, characterized in that the electrically erasable memory is subdivided into several subareas and that a subarea write protect flip-flop means is associated with each of the several subareas.
Claim 5
Dependent Claim
27 words
Method according to claim 3, characterized in that a main write flip-flop overrides the subarea write protect flip-flop means and actuates the subarea write protect flip-flop means.
Claim 6
Dependent Claim
136 words
A electrically erasable memory which is connected to a microprocessor comprising at least one write-protect flip-flop means whose two respective logical states signify "with write protection" and "without write protection", at least one gate in a writing line of said electrically erasable memory being controlled by said write-protect flip-flop means and the at least one gate in response to logical "with write protection" state thereupon blocks passage of writing commands to individual storage cells of said memory, and a mechanical switching means being coupled at one input to said write-protect flip-flop means, such that said flip-flop means can only be brought by said microprocessor into the one logical state "with write protection" state, whereas said flip-flop means can only be brought into the other logical "without write protection" state when said mechanical switching means is actuated.
Claim 7
Dependent Claim
136 words
A electrically erasable memory which is connected to a microprocessor comprising at least one write-protect flip-flop means whose two respective logical states signify "with write protection" and "without write protection", at least one gate in a writing line of said electrically erasable memory being controlled by said write-protect flip-flop means and the at least one gate in response to logical "with write protection" state thereupon blocks passage of writing commands to individual storage cells of said memory, and a mechanical switching means being coupled at one input to said write-protect flip-flop means, such that said flip-flop means can only be brought by said microprocessor into the one logical state "with write protection" state, whereas said flip-flop means can only be brought into the other logical "without write protection" state when said mechanical switching means is actuated.
Claim 8
Dependent Claim
27 words
An electrically erasable memory in accordance with claim 5, including a separate, individual write-protect flip-flop means associated with an individual memory subarea of said electrically erasable memory.
Claim 9
Dependent Claim
44 words
An electrically erasable memory in accordance with claim 5, including a separate subarea write-protect flip-flop means associated with an individual memory subarea of the electrically erasable memory that controls all of the separate subarea write-protect flip-flop means by a single main write-protect flip-flop means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |