Method for forming a multilayered metal network for bonding components of a high-density integrated circuit, and integrated circuit produced thereby

Claim 1

In a method of forming a multilayered metal network for interconnecting components of a high-density integrated circuit, the network comprising a lower metal layer including conductors having steep edges formed over a substrate, a method of obtaining a planar surface over said lower metal layer comprising applying a layer of spin-on-glass over said lower metal layer, said spin-on-glass layer being applied to have a thickness substantially equal to that of the lower metal layer and to form a thin film over said conductors; uniformly etching said spin-on-glass layer to expose upper surfaces of said conductors of the lower metal layer; and applying a dielectric layer onto the etched spin-on-glass layer and said upper surfaces of the conductors.

Claim 10

A method of forming a multilayered metal network for interconnecting components of a highdensity integrated circuit, comprising forming over a substrate a lower metal layer including conductors having steep edges; spreading a layer of spin-on-glass in the form of a viscous suspension of silicon dioxide on said lower metal layer; annealing said spin-on-glass layer, said spin-on-glass layer having a thickness substantially equal to said conductors; uniformly etching using a reactive plasma etch process said spin-on-glass layer to expose upper surfaces of said conductors of the lower metal layer; applying using chemical vapor deposition a dielectric layer of silicon dioxide over the etched spin-on-glass layer and the exposed upper surfaces of the conductors of the lower metal layer; forming vias through said dielectric layer by using a reactive plasma etch process so as to flare said vias and provide the vias with a frusto-conical shape for exposing portions of said upper surfaces of said conductors; and covering said dielectric layer while filling said vias with an upper metal layer.

Claim 11

A method of forming a multilayered metal network for interconnecting components of a highdensity integrated circuit, comprising forming over a substrate a lower metal layer including conductors having steep edges; spreading a layer of spin-on-glass in the form of a viscous suspension of silicon dioxide on said lower metal layer; annealing said spin-on-glass layer, said spin-on-glass layer having a thickness substantially equal to said conductors; uniformly etching using a reactive plasma etch process said spin-on-glass layer to expose upper surfaces of said conductors of the lower metal layer; applying using chemical vapor deposition a dielectric layer of silicon dioxide over the etched spin-on-glass layer and the exposed upper surfaces of the conductors of the lower metal layer; forming vias through said dielectric layer by using a reactive plasma etch process so as to flare said vias and provide the vias with a frusto-conical shape for exposing portions of said upper surfaces of said conductors; and covering said dielectric layer while filling said vias with an upper metal layer.