Self-aligned split gate EPROM

Claim 1

An EPROM array comprising: a substrate composed of semiconductor material; a plurality of memory cells formed on the substrate, each memory cell including a split gate transistor; a metal source contact line running in a first direction across the array; a source diffusion line having a multiplicity of portions serving as source regions of the split gate transistors, the source diffusion line being integrally formed in the substrate and running a selected distance across said array orthogonal to said metal source contact line; a contact between said metal source contact line and the source diffusion line for coupling a potential on said metal source contact line to each of said source regions; a plurality of metal drain lines running across said array substantially parallel to said metal source contact line each metal drain line contacting drain region of a selected number of the split gate transistors in said array; a plurality of control lines formed over said array running orthogonal to said metal source contact line and said plurality of metal drain lines; wherein each split gate transistor comprises: a channel region; a floating gate formed over but insulated from a first portion of the channel region, a first edge of the floating gate being aligned with and used to define one edge of the drain region of the split gate transistor, a second edge of said floating gate being over said channel region, the second edge being positioned away from the first edge of the floating gate by a predetermined distance and separated from the closest edge of the source region of the transistor by a second portion of said channel region, and a control gate formed over but insulated from said floating gate and formed over but insulated from said second portion of said channel region; and wherein said control gate of each split gate transistor comprises part of one of said plurality of control lines.