US4870346A
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Distributed pseudo random sequence control with universal polynomial function generator for LSI/VLSI test systems
Assignee: Texas Instruments Inc
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Filing: 1987-09-14
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Granted: 1989-09-26
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Expires: 2007-09-14
Abstract
Abstract Simple polynomial function generators are used to generate pseudo random test patterns and perform signature analysis on a per pin basis in the control logic in LSI/VLSI test systems.
Inventors
- 👤 Marc R. Mydill
- 👤 Theo J. Powell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:13
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318385; G01R31/31813; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
188 words
In a test system for testing a large integrated circuit device under test having plural input and plural output pins, a distributed pseudo random test pattern generation and encoded response analysis system having a clock input for use with said device under test, said distributed pseudo random test pattern generation and encoded response analysis system comprising for each of said input and output pins: a universal polynomial function generator coupled to a predetermined one of said input pins and a predetermined one of said output pins of said device under test, a first gate circuit for connecting said function generator to at least one of said input pins of said device under test, a second gate circuit for connecting said function generator to said predetermined one of said output pins of said device under test, a third gate circuit for interconnecting a clock input of said function generator to one of a plurality of clock/timing signals, and a stage select circuit for configuring said function generator a plurality of NAND circuits connected to a plurality of input/output terminals of said function generator for cascading several said function generators.
Claim 2
Dependent Claim
188 words
In a test system for testing a large integrated circuit device under test having plural input and plural output pins, a distributed pseudo random test pattern generation and encoded response analysis system having a clock input for use with said device under test, said distributed pseudo random test pattern generation and encoded response analysis system comprising for each of said input and output pins: a universal polynomial function generator coupled to a predetermined one of said input pins and a predetermined one of said output pins of said device under test, a first gate circuit for connecting said function generator to at least one of said input pins of said device under test, a second gate circuit for connecting said function generator to said predetermined one of said output pins of said device under test, a third gate circuit for interconnecting a clock input of said function generator to one of a plurality of clock/timing signals, and a stage select circuit for configuring said function generator a plurality of NAND circuits connected to a plurality of input/output terminals of said function generator for cascading several said function generators.
Claim 3
Dependent Claim
30 words
The analysis system according to claim 1, wherein the function generator is a universal polynomial function generator configurable to generate a polynomial to any bit length and any characteristic polynomial.
Claim 4
Dependent Claim
26 words
The analysis system according to claim 1, wherein said first gate supplies inputs to the device under test from any one of at least three sources.
Claim 5
Dependent Claim
26 words
The analysis system according to claim 3, wherein said at least three sources include a parallel pattern memory, a serial pattern memory, and the analysis system.
Claim 6
Dependent Claim
24 words
The analysis system according to claim 1, wherein said second gate outputs data from the device under test to at least three different devices.
Claim 7
Dependent Claim
28 words
The analysis system according to claim 5, wherein the three different devices include a stage select circuit, a universal polynomial function generator, and a receive logic comparison circuit.
Claim 8
Dependent Claim
18 words
The analysis system according to claim 1, wherein said function generator is a programmable linear feedback shift register.
Claim 9
Dependent Claim
21 words
The analysis system according to claim 1, wherein said function generator includes circuitry to select a polynomial of a desired degree.
Claim 10
Dependent Claim
18 words
The analysis system according to claim 1, wherein said function generator includes circuitry to select feedback term select.
Claim 11
Dependent Claim
21 words
The analysis system according to claim 1, wherein said function generator includes circuitry to generate a pseudo random serial pattern output.
Claim 12
Dependent Claim
21 words
The analysis system according to claim 1, wherein said function generator includes circuitry to support serial and parallel signature analysis input.
Claim 13
Dependent Claim
17 words
The analysis system according to claim 1, wherein said function generator includes circuitry to support signature comparison.
Claim 14
Dependent Claim
162 words
In a test system for testing a large integrated circuit device under test having input pins for receiving input test signals and output pins for providing an output responsive to said input test signals indicative of device under test operation, a distributed pseudo random test pattern generation and encoded response analysis circuit for use with a device under test, said distributed pseudo random test pattern generation and encoded response analysis circuit comprising for each of said input and output pins: a universal polynomial function generator, an input circuit connecting said function generator to a said input pin of said device under test, a clock select gate for inputting at least one of plural different clock signals to said function generator, an output circuit connected to a said output pin of said device under test, and a stage select circuit connected to said output circuit and said universal polynomial function generator to vary inputs from said device under test to said function generator.
Claim 15
Dependent Claim
162 words
In a test system for testing a large integrated circuit device under test having input pins for receiving input test signals and output pins for providing an output responsive to said input test signals indicative of device under test operation, a distributed pseudo random test pattern generation and encoded response analysis circuit for use with a device under test, said distributed pseudo random test pattern generation and encoded response analysis circuit comprising for each of said input and output pins: a universal polynomial function generator, an input circuit connecting said function generator to a said input pin of said device under test, a clock select gate for inputting at least one of plural different clock signals to said function generator, an output circuit connected to a said output pin of said device under test, and a stage select circuit connected to said output circuit and said universal polynomial function generator to vary inputs from said device under test to said function generator.
Claim 16
Dependent Claim
30 words
The analysis system according to claim 13, including a data buffer connected to the function generator for receiving data to configure the analysis system as a pseudo random pattern generator.
Claim 17
Dependent Claim
30 words
The analysis system according to claim 13, including a data buffer connected to the function generator for receiving data to configure the analysis system as a signature analysis program system.
Claim 18
Dependent Claim
26 words
The analysis system according to claim 13, including gate circuits for cascading several function generators to encode a series of responses from multiple devices under test.
Claim 19
Dependent Claim
29 words
The analysis system according to claim 13, wherein the clock select gate allows synchronization with other test pattern sources and facilitates dynamic mixing of stored and pseudo random patterns.
Claim 20
Dependent Claim
24 words
The analysis system according to claim 13, wherein the analysis circuit and device under test may be connected for pseudo random serial scan testing.
Claim 21
Dependent Claim
23 words
The analysis system according to claim 13, wherein the analysis circuit and device under test may be connected for simultaneous scan path testing.
Claim 22
Dependent Claim
27 words
The analysis system according to claim 13, wherein the analysis system and device under test may be connected for parallel deterministic device inputs with response data compression.
Claim 23
Dependent Claim
36 words
The analysis system according to claim 13, wherein the analysis circuit and device under test may be connected for mixed testing with pattern and pseudo random pattern generation and serial signature analysis and stored pattern comparison.
Claim 24
Dependent Claim
123 words
In a test system for testing a large integrated circuit device under test having input pins and output pins, a distributed pseudo random test pattern generation and encoded response analysis system for use with said device under test, said distributed pseudo random test pattern generation and encoded response analysis system comprising for each of said input and output pins: a universal polynomial function generator coupled to a predetermined one of said input pins and a predetermined one of said output pins of said device under test, a first gate circuit for connecting said function generator to said input pin of said device under test, and a second gate circuit for connecting said function generator to said output pin of said device under test.
Claim 25
Dependent Claim
123 words
In a test system for testing a large integrated circuit device under test having input pins and output pins, a distributed pseudo random test pattern generation and encoded response analysis system for use with said device under test, said distributed pseudo random test pattern generation and encoded response analysis system comprising for each of said input and output pins: a universal polynomial function generator coupled to a predetermined one of said input pins and a predetermined one of said output pins of said device under test, a first gate circuit for connecting said function generator to said input pin of said device under test, and a second gate circuit for connecting said function generator to said output pin of said device under test.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-25 | 1993-03-27 | 1993-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-25 | 1997-03-27 | 1997-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-25 | 2001-03-27 | 2001-09-26 | $7700.00 | Window Closed / Lapsed |