ESD low resistance input structure

Claim 2

A circuit comprising: an input terminal for receiving an input signal; a first supply terminal for receiving a first supply voltage; a second supply terminal for receiving a second supply voltage; and a first clamp circuit for clamping the voltage level on said input terminal to a voltage in excess of said first supply voltage, thereby preventing said voltage level from exceeding a predefined magnitude in a first polarity defined by said first supply voltage minus said second supply voltage, said first clamp circuit being connected between said input terminal and said first supply terminal, said first clamp circuit comprising a reduced beta bipolar transistor having a first current handling terminal connected to said first supply terminal and a second current handling terminal connected to said input terminal.

Claim 3

A circuit as in claim 1 wherein said first clamp circuit serves to clamp said input terminal from positive-going pulses.

Claim 4

A circuit as in claim 1 wherein said reduced beta bipolar transistor is constructed as a fuse device.

Claim 5

A structure as in claim 3 wherein said fuse device is constructed to have a low impedance and a current handling capability within the range of approximately 150 to 200 milliamps.

Claim 6

A structure as in claim 1 wherein said reduced beta bipolar transistor comprises: an emitter serving as one of said first and second current handling terminals; a collector serving as the other of said first and second current handling terminals; a base; and a current handling path connected between said base and said emitter.

Claim 7

A circuit as in claim 5 wherein said current path comprises a resistor.

Claim 8

A circuit as in claim 1 wherein said first current handling terminal comprises the emitter of a bipolar transistor and said second current handling terminal comprises the collector of said bipolar transistor.

Claim 9

A circuit as in claim 7 wherein said bipolar transistor comprises an NPN transistor.

Claim 10

A circuit as in claim 1 which further includes a second clamp circuit connected between said input terminal and said second supply terminal for clamping the voltage level on said input terminal in a second polarity opposite said first polarity.

Claim 11

A circuit as in claim 1 wherein said second current handling terminal is connected to said input terminal through a diode.

Claim 12

A structure as in claim 10 wherein said reduced beta bipolar transistor and said diode are constructed in an integrated fashion, without the use of metallic contacts.

Claim 13

A structure as in claim 10 wherein said first supply voltage is approximately 4.5 volts, said first clamp circuit has a clamp voltage of approximately 7.7 volts, and said diode provides a voltage drop of aproximately 0.8 volts, whereby said voltage level on said input terminal is clamped to approximately 13 volts.

Claim 14

A circuit as in claim 10 wherein said diode serves to prevent current from flowing between said input terminal and said first supply terminal when said input terminal is connected to said second supply voltage.

Claim 15

A circuit comprising: an input terminal for receiving an input signal; a first supply terminal for receiving a first supply voltage V cc ; a second supply terminal for receving a second supply voltage; and a first clamp circuit connected between said input terminal and said first supply terminal for clamping input signals of a first polarity defined by said first supply voltage minus said second supply voltage to a desired level V CL in excess of said first supply voltage, said first clamp circuit comprising: a diode connected between said input terminal and said first supply terminal to prevent current from flowing between said input terminal and said first supply terminal when said input terminal is connected to said second supply voltage; clamping means having a first and second current handling terminals and comprising a reduced beta transistor connected in series with said diode for providing an input terminal clamping voltage such that V.sub.CL =V.sub.D +V.sub.T +V.sub.cc ; where V CL =the input terminal clamping voltage; V D =the forward bias voltage drop of said diode; V T =the voltage drop across said clamping means; and V cc =said first supply voltage.

Claim 16

A circuit comprising: an input terminal for receiving an input signal; a first supply terminal for receiving a first supply voltage V cc ; a second supply terminal for receving a second supply voltage; and a first clamp circuit connected between said input terminal and said first supply terminal for clamping input signals of a first polarity defined by said first supply voltage minus said second supply voltage to a desired level V CL in excess of said first supply voltage, said first clamp circuit comprising: a diode connected between said input terminal and said first supply terminal to prevent current from flowing between said input terminal and said first supply terminal when said input terminal is connected to said second supply voltage; clamping means having a first and second current handling terminals and comprising a reduced beta transistor connected in series with said diode for providing an input terminal clamping voltage such that V.sub.CL =V.sub.D +V.sub.T +V.sub.cc ; where V CL =the input terminal clamping voltage; V D =the forward bias voltage drop of said diode; V T =the voltage drop across said clamping means; and V cc =said first supply voltage.

Claim 17

A circuit as in claim 14 wherein said reduced beta bipolar transistor is constructed as a fuse device.

Claim 18

A structure as in claim 15 wherein said fuse device is constructed to have a low impedance and a current handling capability within the range of approximately 150 to 200 milliamps.

Claim 19

A structure as in claim 14 wherein said reduced beta transistor comprises: an emitter serving as one of said first and second current handling terminals; a collector serving as the other of said first and second current handling terminals; a base; and a current handling path connected between said base and said emitter.

Claim 20

A circuit as in claim 14 wherein said current path comprises a resistor.

Claim 21

A circuit as in claim 14 wherein said first current handling terminal comprises the emitter of a bipolar transistor and said second current handling terminal comprises the collector of said bipolar transistor.

Claim 22

A circuit as in claim 19 wherein said bipolar transistor comprises an NPN transistor.

Claim 23

A circuit as in claim 14 wherein said first clamp circuit serves to clamp said input terminal from positive-going pulses.

Claim 24

A circuit as in claim 14 which further includes a second clamp circuit connected between said input terminal and a second supply terminal for clamping the voltage level on said input terminal in a second polarity opposite said first polarity.

Claim 25

A structure as in claim 14 wherein said reduced beta bipolar transistor and said diode are constructed in an integrated fashion, without the use of metallic contacts.