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US4930002A
Expired / Lapsed
US
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Multi-chip module structure
Assignee: Hitachi Ltd
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Filing: 1988-03-22
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Granted: 1990-05-29
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Expires: 2008-03-22
Abstract
Abstract In a pin grid array type multi-chip module structure comprised of a ceramic multi-layer wiring board having the top surface on which a plurality of semiconductor devices are carried, divisional board areas each having the same size are respectively allotted to individual semiconductor devices of the same type. Within respective divisional board areas, the positional relation between the array arrangement of connecting pads on the top surface for connection to the semiconductor devices and the array arrangement of I/O pins on the bottom surface of the board is so determined as to be constant. Metallized patterns inside the board which are to be connected power supply I/O pins and ground I/O pins are made constant for respective divisional board areas allotted to individual semiconductor devices of the same type.
Inventors
- 👤 Takaji Takenaka
- 👤 Tositada Netsu
- 👤 Hidetaka Shigi
- 👤 Masakazu Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:42
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H10W70/67; H10W70/68; H10W70/685; H10W72/00; H10W72/01; H10W72/0198; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
185 words
A pin grid array type multi-chip module structure comprising: a ceramic multi-layer wiring board having opposing first and second surfaces; a plurality of connecting pads arrayed on said first surface to mount a plurality of semiconductor devices on said first surface; a plurality of through-holes within said board; a plurality of I/O pins arrayed on said second surface including power supply pins and signal pins, wherein a predetermined area of said board is divided into a plurality of divisional board areas each having the same size, each of said divisional board areas being allotted to individual semiconductor devices of a same type, said connecting pads, said through-holes and said I/O pins being supplied equally to each of said divisional board areas, and wherein positional relationships between said connecting pads, said through-holes and said I/O pins are substantially identical for each divisional board area; and, a plurality of selected layers, wherein said selected layers include metallized patterns for supplying power inside said board, said patterns being connectable to said power supply pins via said through-holes whereby said patterns are made constant for each divisional board area.
Claim 2
Dependent Claim
185 words
A pin grid array type multi-chip module structure comprising: a ceramic multi-layer wiring board having opposing first and second surfaces; a plurality of connecting pads arrayed on said first surface to mount a plurality of semiconductor devices on said first surface; a plurality of through-holes within said board; a plurality of I/O pins arrayed on said second surface including power supply pins and signal pins, wherein a predetermined area of said board is divided into a plurality of divisional board areas each having the same size, each of said divisional board areas being allotted to individual semiconductor devices of a same type, said connecting pads, said through-holes and said I/O pins being supplied equally to each of said divisional board areas, and wherein positional relationships between said connecting pads, said through-holes and said I/O pins are substantially identical for each divisional board area; and, a plurality of selected layers, wherein said selected layers include metallized patterns for supplying power inside said board, said patterns being connectable to said power supply pins via said through-holes whereby said patterns are made constant for each divisional board area.
Claim 3
Dependent Claim
21 words
A multi-chip module structure according to claim 1, wherein said power supply pins includes power voltage supply pins and grounding pins.
Claim 4
Dependent Claim
215 words
A multi-chip module structure according to claim 1, wherein said selected layers include: a top layer having said connecting pads for mounting said semiconductor devices on said first surface; an expansion layer connected to another surface of said top layer, for transferring the grid pitch of said connecting pads to the grid pitch of through-holes inside said board; a conversion layer for transferring the grid pitch of said through holes inside said board to the grip pitch of said I/O pins; a bottom layer having pads for connection to said I/O pins on said second surface, another surface of said bottom layer being connected to said conversion layer; and pairs of signal wiring layers and power supply layers wherein said signal wiring layers a not one at said selected layers, said pairs being stacked on each other such that the signal wiring layer and the power supply layer are disposed alternately, said pairs being inserted between said expansion layer and said conversion layer, wherein in each pair, said signal wiring layer provides wiring between said semiconductor devices, said power supply layer having a predetermined metallized pattern in the divisional area dedicated to each of the semiconductor devices of the same type, to perform matching of characteristic impedances of signal conductors on said signal wiring layers.
Claim 5
Dependent Claim
114 words
A multi-chip module structure according to claim 1, having another predetermined area of said board divided into a plurality of divisional board areas each having another size, and each of said another-sized divisional board areas being allotted to semiconductor devices of another type, said connecting pads, said through-holes and said I/O pins being supplied equally to each of said another-sized divisional board areas, positional relationships between said connecting pads, said through-holes and said I/O pins being made identical for every another-sized divisional board area and metallized patterns for supplying power inside said board connected to said power supply pins via the through-holes said metallized patterns being made constant for every another-sized divisional board area.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-28 | 1993-11-27 | 1994-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-28 | 1997-11-27 | 1998-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-28 | 2001-11-27 | 2002-05-29 | $7700.00 | Window Closed / Lapsed |