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US4933879A
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US
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Multi-plane video RAM
Assignee: Fujitsu Ltd
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Filing: 1988-02-18
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Granted: 1990-06-12
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Expires: 2008-02-18
Abstract
Abstract A multi-plane video RAM for displaying a color image on a display apparatus. A multi-plane bit operation unit is used for calculating input data from an external stage based on a predetermined rule corresponding to an information applied from the external stage. Memory arrays are operatively connected to the multi-plane bit operation unit for writing resultant data calculated by the multi-plane bit operation unit. Each array having three-dimensionally arranged k sets of memory planes each consisting of m (rows)×n (columns); wherein the same corresponding positions of the k sets of memory planes are simultaneously accessed and the resultant data calculated by the multi-plane bit operation unit are also simultaneously written thereto.
Inventors
- 👤 Hisashige Ando
- 👤 Saburo Sasanuma
- 👤 Takahiro Sakuraba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:12
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/02; G09G5/022; G09G5/36; G09G5/39; G09G5/393
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
176 words
A multi-plane video RAM for receiving information and displaying a color image on a display apparatus, comprising: multi-plane bit operation means for calculating and input data based on a predetermined rule corresponding to the received information and for providing resultant data responsive to said calculating, said multi-plane bit operation means including first k bit register means for storing a first portion of the received information and for providing a first portion of the input data based on said first portion of the received information, and second k bit register means for storing a second portion of the received information and for providing a second portion of the input data based on said second portion of the received information; memory array means, operatively connected to said multi-plane bit operation means, for receiving and storing said resultant data, and said memory array means including three-dimensionally arranged k sets of memory planes, each plane having m (rows)×n (columns); and means for simultaneously accessing corresponding positions of said k sets of memory planes and for writing said resultant data thereto.
Claim 2
Dependent Claim
176 words
A multi-plane video RAM for receiving information and displaying a color image on a display apparatus, comprising: multi-plane bit operation means for calculating and input data based on a predetermined rule corresponding to the received information and for providing resultant data responsive to said calculating, said multi-plane bit operation means including first k bit register means for storing a first portion of the received information and for providing a first portion of the input data based on said first portion of the received information, and second k bit register means for storing a second portion of the received information and for providing a second portion of the input data based on said second portion of the received information; memory array means, operatively connected to said multi-plane bit operation means, for receiving and storing said resultant data, and said memory array means including three-dimensionally arranged k sets of memory planes, each plane having m (rows)×n (columns); and means for simultaneously accessing corresponding positions of said k sets of memory planes and for writing said resultant data thereto.
Claim 3
Dependent Claim
31 words
A multi-plane video RAM as claimed in claim 1, wherein numbers of k and n of said three-dimensionally arranged k sets of memory planes are given by a power of two.
Claim 4
Dependent Claim
57 words
A multi-plane video RAM as claimed in claim 1, wherein said multi-plane bit operation means comprises: third register means, having a k bit length, for enabling data stored in said first and second register means to be written into a selected memory plane, and for maintaining other bits except for said written bits at a previous state.
Claim 5
Dependent Claim
57 words
A multi-plane video RAM as claimed in claim 1, wherein said multi-plane bit operation means includes: means for providing logic calculations with at least some of said received information and with said data stored in said first and second register means, and for writing resultant data from said logic calculation to corresponding position in said memory plane.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-11 | 1993-12-11 | 1994-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-11 | 1997-12-11 | 1998-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-11 | 2001-12-11 | 2002-06-12 | $7700.00 | Window Closed / Lapsed |