Patent US4948748A successfully refreshed from Google Patents.
US4948748A
Expired / Lapsed
US
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Manufacture of a substrate structure for a composite semiconductor device using wafer bonding and epitaxial refill
Assignee: Toshiba Corp
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Filing: 1989-08-21
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Granted: 1990-08-14
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Expires: 2009-08-21
Abstract
Abstract A substrate structure for a composite semiconductor device comprises first and second semiconductor substrates whose major surfaces are bonded to each other with an insulating layer interposed therebetween. In this substrate structure, an epitaxial layer is grown from part of the second semiconductor substrate, forming one element area, and another element area is formed in the first semiconductor substrate area and isolated from the epitaxial layer.
Inventors
- 👤 Koichi Kitahara
- 👤 Yu Ohata
- 👤 Tsuyoshi Kuramoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:13
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/018; H10W10/061; H10W10/10; H10W10/181; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10P90/1912; H10P90/1914; H10W10/041; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/135
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
107 words
A method of making a substrate structure for a composite semiconductor device comprising the steps of: (a) mirror-finishing a surface of each first and second semiconductor substrate; (b) forming by thermal oxidation an insulating film on the mirror-finished surfaces of the first and second semiconductor substrates; (c) bonding together the mirror finished surfaces of the first and second semiconductor substrates with the insulating film interposed between the bonded mirror-finished surfaces; (d) etching through a portion of the first semiconductor substrate and the insulating film to reach at least the second semiconductor substrate; and (e) forming an epitaxial layer on the second semiconductor substrate in the etched area.
Claim 2
Independent Claim
107 words
A method of making a substrate structure for a composite semiconductor device comprising the steps of: (a) mirror-finishing a surface of each first and second semiconductor substrate; (b) forming by thermal oxidation an insulating film on the mirror-finished surfaces of the first and second semiconductor substrates; (c) bonding together the mirror finished surfaces of the first and second semiconductor substrates with the insulating film interposed between the bonded mirror-finished surfaces; (d) etching through a portion of the first semiconductor substrate and the insulating film to reach at least the second semiconductor substrate; and (e) forming an epitaxial layer on the second semiconductor substrate in the etched area.
Claim 3
Dependent Claim
66 words
The method of claim 1, further comprising the steps of: (a) forming an element isolation area in the first semiconductor substrate in an area distinct from the epitaxial layer of the composite substrate unit, the element isolation area reaching the insulating film on the first semiconductor substrate, and (b) forming an element area in the first semiconductor substrate area being electrically isolated from the epitaxial area.
Claim 4
Dependent Claim
18 words
The method of claim 2, wherein a plurality of element areas are formed in the first semiconductor substrate.
Claim 5
Dependent Claim
21 words
The method of claim 1, wherein the epitaxial layer has a thickness substantially equal to that of the first semiconductor substrate.
Claim 6
Dependent Claim
22 words
The method of claim 1, wherein the thickness of the epitaxial layer is substantially greater than that of the first semiconductor substrate.
Claim 7
Dependent Claim
27 words
The method of claim 2, wherein the epitaxial layer has an impurity concentration level different from that of the element isolation area of the first semiconductor substrate.
Claim 8
Dependent Claim
39 words
The method of claim 2, further comprising the steps of: (a) forming a power element in the epitaxial layer, and (b) forming semiconductor elements in the element isolation areas of the first semiconductor substrate to control the power element.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |