Process for defining vias through silicon nitride and polyamide

Claim 1

In an integrated circuit chip having a plurality of semiconductor devices, a process for defining self-aligned vias through a silicon nitride layer and a polyimide layer comprising the following steps in the following order: depositing a layer of silicon nitride over said semiconductor devices, said silicon nitride layer having a thickness in the range 0.2-1.0 microns; depositing a layer of polyimide over said silicon nitride layer, said polyimide layer having a thickness greater than said silicon nitride layer and being in the range 0.6-2.5 microns; depositing a layer of photoresist capable of forming sidewalls having a negative profile over said polyimide layer, said layer of photoresist having a thickness greater than said polyimide layer; patternwise exposing said photoresist layer to radiation; developing the exposed photoresist layer to form an image having negatively sloped sidewalls; etching the silicon nitride layer with a mixture of CF 4 and O 2 using the patterned photoresist layer as an etch mask; and etching the silicon nitride layer with a mixture of CF 4 and H 2 , using the etched polyimide layer as an etch mask.