Packaged semiconductor device having a low cost ceramic PGA package

Claim 2

A packaged semiconductor device comprising: a single-layer ceramic base having a first plurality of through-holes therein; an integrated circuit disposed at a predetermined location on said base; terminal means attached to said base extending through said first plurality of through-holes in said base and having distal ends extending therefrom, said terminal means providing external electrical connection to said semiconductor device; a cap substantially co-extensive with said base having a second plurality of through-holes therein corresponding with and aligned to said first plurality of through-holes in said base, said cap bonded to said base forming a cavity between said base and said cap hermetically enclosing said integrated circuit within said cavity; and coupling means for electrically coupling said terminal means to said integrated circuit.

Claim 3

The packaged semiconductor device of claim 1 wherein said coupling means comprises: patterned metal leads disposed on said base projecting outwardly from said cavity and forming an electrical contact with said terminal means; and metal interconnect leads electrically connected to said integrated circuit and bonded to said outwardly projecting patterned metal leads.

Claim 4

The packaged semiconductor device of claim 2 wherein said patterned metal leads overlie the surface of said first plurality of through-holes in said base.

Claim 5

The packaged semiconductor device of claim 3 wherein said terminal means comprise swaged I/O pins extending through said first plurality of through-holes in said base and spaced apart from said base by said patterned metal leads, each of said pins having a pin head situated above said base and a pin bulge situated below said base.

Claim 6

The packaged semiconductor device of claim 2 wherein said metal interconnect leads comprise wire bonds.

Claim 7

The packaged semiconductor device of claim 2 wherein said metal interconnect leads comprise TAB bonds.

Claim 8

The packaged semiconductor device of claim 1 wherein said cap is bonded to said insulating base by a layer of Pb-borosilicate glass disposed between said insulating cap and said insulating base.

Claim 9

The packaged semiconductor device of claim 1 wherein said cap further comprises an indented surface portion aligned with said integrated circuit disposed on said base forming a cavity between said base and said cap, said cavity in confronting relation to said integrated circuit.

Claim 10

A packaged semiconductor device comprising: a single-layer ceramic base having a first plurality of through-holes therein; an integrated circuit disposed at a predetermined location on said base; a plurality of I/O pins extending through said first plurality of through-holes in said base and mechanically attached to said base and having distal ends extending therefrom; a cap substantially co-extensive with said base having a second plurality of of through-holes therein aligned to said first plurality of through-holes in said base engaging said distal ends of said I/O pins and bonded said base forming a cavity between said base and said cap hermetically enclosing said integrated circuit within said cavity; and means electrically coupling said I/O pins to said integrated circuit.

Claim 11

A packaged semiconductor device comprising: a single-layer ceramic base having a first plurality of through-holes therein; an integrated circuit disposed at a predetermined location on said base; a plurality of I/O pins extending through said first plurality of through-holes in said base and mechanically attached to said base and having distal ends extending therefrom; a cap substantially co-extensive with said base having a second plurality of of through-holes therein aligned to said first plurality of through-holes in said base engaging said distal ends of said I/O pins and bonded said base forming a cavity between said base and said cap hermetically enclosing said integrated circuit within said cavity; and means electrically coupling said I/O pins to said integrated circuit.

Claim 12

The packaged semiconductor device of claim 9 wherein said means electrically coupling said I/O pins to said integrated circuit comprises: patterned metal leads disposed on said base projecting outwardly from said cavity and forming an electrical contact with said I/O pins; and metal interconnect leads electrically connected to said integrated circuit and bonded to said outwardly projecting patterned metal leads.

Claim 13

The packaged semiconductor device of claim 10 wherein said patterned metal leads overlie the surface of said first plurality of through-holes in said base.

Claim 14

The packaged semiconductor device of claim 10 wherein said metal interconnect leads comprise wire bonds.

Claim 15

The packaged semiconductor device of claim 10 wherein said metal interconnect leads comprise TAB bonds.

Claim 16

The packaged semiconductor device of claim 9 wherein said cap is bonded to said insulating base by a layer of Pb-borosilicate glass disposed between said insulating cap and said insulating base.

Claim 17

The packaged semiconductor device of claim 9 wherein said cap further comprises an indented surface portion aligned with said integrated circuit disposed on said base forming a cavity between said base and said cap, said cavity in confronting relation to said integrated circuit.

Claim 18

A packaged semiconductor device comprising: a single-layer ceramic base having a first plurality of through-holes therein; an integrated circuit having a plurality of bonding pads thereon and mounted to said base at a predetermined location; a plurality of I/O pins extending through said first plurality of through-holes in said base, said plurality of I/O pins mechanically attached to said base and having distal ends extending therefrom; a cap substantially co-extensive with said base having a second plurality of of through-holes therein aligned to said first plurality of through-holes in said base, said cap bonded to said base forming a cavity between said base and said cap hermetically enclosing said integrated circuit within said cavity; patterned metal leads disposed on said base projecting outwardly from said cavity to said first plurality of through-holes in said base, said patterned metal leads extending into said first plurality of through-holes forming an electrical contact to said I/O pins; and a series of metal interconnect leads electrically connected to said bonding pads of said integrated circuit at one end and electrically connected to said patterned metal leads at the other end.

Claim 19

A packaged semiconductor device comprising: a single-layer ceramic base having a first plurality of through-holes therein; an integrated circuit having a plurality of bonding pads thereon and mounted to said base at a predetermined location; a plurality of I/O pins extending through said first plurality of through-holes in said base, said plurality of I/O pins mechanically attached to said base and having distal ends extending therefrom; a cap substantially co-extensive with said base having a second plurality of of through-holes therein aligned to said first plurality of through-holes in said base, said cap bonded to said base forming a cavity between said base and said cap hermetically enclosing said integrated circuit within said cavity; patterned metal leads disposed on said base projecting outwardly from said cavity to said first plurality of through-holes in said base, said patterned metal leads extending into said first plurality of through-holes forming an electrical contact to said I/O pins; and a series of metal interconnect leads electrically connected to said bonding pads of said integrated circuit at one end and electrically connected to said patterned metal leads at the other end.

Claim 20

The packaged semiconductor device of claim 16 wherein said metal interconnect leads comprise wire bonds.

Claim 21

The packaged semiconductor device of claim 16 wherein said metal interconnect leads comprise TAB bonds.

Claim 22

A packaged semiconductor device comprising: a single-layer ceramic base having a first plurality of through-holes therein; an integrated circuit disposed at a predetermined location on said base; a plurality of I/O pins extending through said first plurality of through-holes in said base and mechanically attached to said base and having distal ends extending therefrom; a cap overlying said base and substantially co-extensive with said base having a second plurality of of through-holes therein aligned to said first plurality of through-holes in said base and bonded to said base forming a cavity between said base and said cap hermetically enclosing said integrated circuit within said cavity; and means electrically coupling said I/O pins to said integrated circuit.

Claim 23

A packaged semiconductor device comprising: a single-layer ceramic base having a first plurality of through-holes therein; an integrated circuit disposed at a predetermined location on said base; a plurality of I/O pins extending through said first plurality of through-holes in said base and mechanically attached to said base and having distal ends extending therefrom; a cap overlying said base and substantially co-extensive with said base having a second plurality of of through-holes therein aligned to said first plurality of through-holes in said base and bonded to said base forming a cavity between said base and said cap hermetically enclosing said integrated circuit within said cavity; and means electrically coupling said I/O pins to said integrated circuit.

Claim 24

The packaged semiconductor device of claim 19 wherein said cap further comprises an indented surface portion aligned with said integrated circuit disposed on said base forming a cavity between said base and said cap, said cavity in confronting relation to said integrated circuit.

Claim 25

The packaged semiconductor device of claim 19 wherein said cap is bonded to said insulating base by a layer of Pb-borosilicate glass disposed between said insulating cap and said insulating base.

Claim 26

The packaged semiconductor device of claim 19 wherein said means electrically coupling said I/O pins to said integrated circuit comprises: patterned metal leads disposed on said base projecting outwardly from said cavity and forming an electrical contact with said I/O pins; and metal interconnect leads electrically connected to said integrated circuit and bonded to said outwardly projecting patterned metal leads.