Patent US5043947A successfully refreshed from Google Patents.
US5043947A
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1990-05-30
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Granted: 1991-08-27
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Expires: 2010-05-30
Abstract
Abstract A memory device is provided including a plurality of memory arrays and peripheral circuits. For example, in a dynamic RAM the peripheral circuitry will include row address decoders, column address decoders, sense amplifiers and main amplifiers disposed in such a manner as to correspond to the memory arrays, respectively. The desired row address decoders, column address decoders, sense amplifiers and main amplifiers are selectively operated in accordance with a common array selection signal generated on the basis of at least part of row address signals. Accordingly, only the row address decoders, column address decoders, sense amplifiers and main amplifiers corresponding to the memory array containing the designated memory cells are operated selectively in accordance with the common array selection signal. It is thus possible to reduce power consumption of the dynamic RAM and to simplify the structure of the peripheral circuits and wirings.
Inventors
- 👤 Kazuyoshi Oshima
- 👤 Takashi Yamazaki
- 👤 Yasuhiro Kasama
- 👤 Tetsu Udagawa
- 👤 Hiroaki Kotani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C8/00; G11C8/12; G11C11/401; G11C11/4063; G11C11/407
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
114 words
A semiconductor memory device comprising: a plurality of memory arrays; row address decoders disposed in such a manner as to correspond to said memory arrays; column address decoders, each of which is disposed in common with memory arrays among said plurality of memory arrays; a plurality of amplifiers disposed in such a manner as to correspond to said memory arrays; and selecting means for generating a signal to selectively operate a predetermined two or more of said row address decoders corresponding to selected memory arrays, a predetermined one of said column address decoders corresponding to said selected memory arrays, and a predetermined two or more of said amplifiers corresponding to said selected memory arrays.
Claim 2
Dependent Claim
114 words
A semiconductor memory device comprising: a plurality of memory arrays; row address decoders disposed in such a manner as to correspond to said memory arrays; column address decoders, each of which is disposed in common with memory arrays among said plurality of memory arrays; a plurality of amplifiers disposed in such a manner as to correspond to said memory arrays; and selecting means for generating a signal to selectively operate a predetermined two or more of said row address decoders corresponding to selected memory arrays, a predetermined one of said column address decoders corresponding to said selected memory arrays, and a predetermined two or more of said amplifiers corresponding to said selected memory arrays.
Claim 3
Dependent Claim
39 words
A semiconductor memory device according to claim 1, wherein said semiconductor memory device is a dynamic RAM and wherein said amplifiers include sense amplifiers and main amplifiers disposed in such a manner as to correspond to said memory arrays.
Claim 4
Dependent Claim
276 words
A semiconductor memory device comprising: a plurality of memory arrays, each including a plurality of memory cells disposed in matrix; a plurality of external terminals for address signals; first and second control external terminals; address signal generation means coupled to said external terminals for address signals and to said first and second external terminals, for generating row address signals in accordance with address signals at said external terminals for said address signals in synchronism with a first strobe signal supplied thereto through said first control external terminal, and for generating column address signals in accordance with address signals at said external terminals for said address signals in synchronism with a second strobe signal supplied thereto through said second control external terminal; a plurality of row address decoders disposed in such a manner as to correspond to said plurality of memory arrays, respectively, for selecting a plurality of memory cells designated by predetermined row address signals among said row address signals from selected memory arrays; a plurality of column address decoders, each disposed in common with memory arrays among said plurality of memory arrays, respectively, for selecting a plurality of memory cells designated by said column address signals from said selected memory array; a plurality of main amplifiers disposed in such a manner as to correspond to said memory arrays; and selection signal generation means for generating a selection signal for operating a predetermined two or more of said row address decoders corresponding to selected memory arrays, a predetermined one of said column address decoders corresponding to said selected memory arrays, and a predetermined two or more of said main amplifiers corresponding to said selected memory arrays.
Claim 5
Dependent Claim
276 words
A semiconductor memory device comprising: a plurality of memory arrays, each including a plurality of memory cells disposed in matrix; a plurality of external terminals for address signals; first and second control external terminals; address signal generation means coupled to said external terminals for address signals and to said first and second external terminals, for generating row address signals in accordance with address signals at said external terminals for said address signals in synchronism with a first strobe signal supplied thereto through said first control external terminal, and for generating column address signals in accordance with address signals at said external terminals for said address signals in synchronism with a second strobe signal supplied thereto through said second control external terminal; a plurality of row address decoders disposed in such a manner as to correspond to said plurality of memory arrays, respectively, for selecting a plurality of memory cells designated by predetermined row address signals among said row address signals from selected memory arrays; a plurality of column address decoders, each disposed in common with memory arrays among said plurality of memory arrays, respectively, for selecting a plurality of memory cells designated by said column address signals from said selected memory array; a plurality of main amplifiers disposed in such a manner as to correspond to said memory arrays; and selection signal generation means for generating a selection signal for operating a predetermined two or more of said row address decoders corresponding to selected memory arrays, a predetermined one of said column address decoders corresponding to said selected memory arrays, and a predetermined two or more of said main amplifiers corresponding to said selected memory arrays.
Claim 6
Dependent Claim
26 words
A semiconductor memory device according to claim 3, wherein each of said memory cells includes a storage capacitor and a switch device for selecting the address.
Claim 7
Dependent Claim
37 words
A semiconductor memory device according to claim 4, wherein a common selection signal is supplied from said selection signal generation means to said row address decoder and to said column address decoder that are to be operated.
Claim 8
Dependent Claim
41 words
A semiconductor memory device according to claim 5, wherein each of said column address decoder and said row address decoder includes a decoder circuit to which a power source voltage is selectively supplied in accordance with a selection signal supplied thereto.
Claim 9
Dependent Claim
118 words
A semiconductor memory device comprising: a plurality of memory arrays; row address decoders disposed in such a manner as to respectively correspond to said memory arrays; column address decoders, each of which is disposed in common with memory arrays among said plurality of memory arrays; and selecting means for generating a signal to selectively operate a predetermined two or more of said row address decoders corresponding to said selected memory arrays, and a predetermined one of said column address decoders corresponding to said selected memory arrays, so that only said predetermined row address decoders and said predetermined column address decoder are operated while row address decoders and column address decoder corresponding to non-selected memory arrays are not operated.
Claim 10
Dependent Claim
118 words
A semiconductor memory device comprising: a plurality of memory arrays; row address decoders disposed in such a manner as to respectively correspond to said memory arrays; column address decoders, each of which is disposed in common with memory arrays among said plurality of memory arrays; and selecting means for generating a signal to selectively operate a predetermined two or more of said row address decoders corresponding to said selected memory arrays, and a predetermined one of said column address decoders corresponding to said selected memory arrays, so that only said predetermined row address decoders and said predetermined column address decoder are operated while row address decoders and column address decoder corresponding to non-selected memory arrays are not operated.
Claim 11
Dependent Claim
17 words
A semiconductor memory device according to claim 7, wherein said semiconductor memory device is a dynamic RAM.
Claim 12
Dependent Claim
18 words
A semiconductor memory device according to claim 8, wherein said address signal is part of row address signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-26 | 1995-02-25 | 1995-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-26 | 1999-02-25 | 1999-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-26 | 2003-02-25 | 2003-08-27 | $7700.00 | Window Closed / Lapsed |