Method of forming an antifuse element with substantially reduced capacitance using the locos technique

Claim 2

In an electrically programmable antifuse element including a dielectric layer between two conductive electrodes, one of said electrodes comprising an implanted region in a semiconductor substrate, a method for forming an antifuse aperture including the steps of: forming a silicon dioxide layer over said implanted region, forming a silicon nitride pad over said silicon dioxide layer, exposing said semiconductor substrate to an oxidizing atmosphere to form an intermediate silicon dioxide layer such that the edges of said intermediate silicon dioxide layer encroach underneath the edges of said silicon nitride pad, removing said silicon nitride pad.

Claim 3

The method according to claim 1 wherein said step of forming a silicon nitride pad includes: forming a first elongate silicon nitride strip disposed substantially over said implanted region, said first elongate silicon nitride strip having a width equal to the minimum feature size in the process technology used to produce it, forming a second elongate silicon nitride strip, said second elongate silicon nitride strip having a width equal to the minimum feature size in the process technology used to produce it, said second silicon nitride strip intersecting said first silicon nitride strip at a location where it is desired to create an antifuse.

Claim 4

In an electrically programmable antifuse element including a dielectric layer between two conductive electrodes, one of said electrodes comprising an implanted region in a semiconductor substrate, a method for forming an antifuse aperture including the steps of: forming a thin silicon dioxide layer over said implanted region, forming a silicon nitride layer overlying said thin silicon dioxide layer, forming a silicon dioxide masking layer over said silicon nitride layer, isotropically etching said dioxide masking layer and said silicon nitride layer to form a silicon nitride pad having an area equal to less than that of said silicon dioxide masking layer, exposing said semiconductor substrate to an oxidizing atmosphere to form an intermediate silicon dioxide layer such that the edges of said intermediate silicon dioxide layer encroach underneath the edges of said silicon nitride pad, removing said silicon dioxide masking layer and said silicon nitride pad.

Claim 5

In an electrically programmable antifuse element including a dielectric layer between two conductive electrodes, one of said electrodes comprising an implanted region in a semiconductor substrate, a method for forming an antifuse aperture including the steps of: forming a thin silicon dioxide layer over said implanted region, forming a silicon nitride layer overlying said thin silicon dioxide layer, forming a silicon dioxide masking layer over said silicon nitride layer, isotropically etching said dioxide masking layer and said silicon nitride layer to form a silicon nitride pad having an area equal to less than that of said silicon dioxide masking layer, exposing said semiconductor substrate to an oxidizing atmosphere to form an intermediate silicon dioxide layer such that the edges of said intermediate silicon dioxide layer encroach underneath the edges of said silicon nitride pad, removing said silicon dioxide masking layer and said silicon nitride pad.

Claim 6

In an electrically programmable antifuse element including a dielectric layer between two conductive electrodes, one of said electrodes comprising an implanted region in a semiconductor substrate, a method for forming an antifuse aperture including the steps of: forming a first thin silicon dioxide layer over said implanted region, forming a polycrystalline silicon layer over said thin silicon dioxide layer, said polycrystalline silicon layer having an area larger than the desired area of said antifuse, forming a silicon nitride pad over said polycrystalline silicon layer, said silicon nitride pad having an area approximately the same size as said polysilicon layer, isotropically etching said silicon nitride pad and said polycrystalline silicon layer, to form a polysilicon pad having an area equal to less than that of said silicon nitride pad, exposing said semiconductor substrate to an oxidizing atmosphere to form an intermediate silicon dioxide layer such that the edges of said intermediate silicon dioxide layer encroach underneath the edges of said polycrystalline silicon pad, removing said polycrystalline silicon pad and said silicon nitride pad.

Claim 7

In an electrically programmable antifuse element including a dielectric layer between two conductive electrodes, one of said electrodes comprising an implanted region in a semiconductor substrate, a method for forming an antifuse aperture including the steps of: forming a first thin silicon dioxide layer over said implanted region, forming a polycrystalline silicon layer over said thin silicon dioxide layer, said polycrystalline silicon layer having an area larger than the desired area of said antifuse, forming a silicon nitride pad over said polycrystalline silicon layer, said silicon nitride pad having an area approximately the same size as said polysilicon layer, isotropically etching said silicon nitride pad and said polycrystalline silicon layer, to form a polysilicon pad having an area equal to less than that of said silicon nitride pad, exposing said semiconductor substrate to an oxidizing atmosphere to form an intermediate silicon dioxide layer such that the edges of said intermediate silicon dioxide layer encroach underneath the edges of said polycrystalline silicon pad, removing said polycrystalline silicon pad and said silicon nitride pad.

Claim 8

The method according to claim 4 wherein said step of forming a silicon nitride pad includes: forming a first elongate silicon nitride strip disposed substantially over said implanted region, said first elongate silicon nitride strip having a width equal to the minimum feature size in the process technology used to produce it, forming a second elongate silicon nitride strip, said second elongate silicon nitride strip having a width equal to the minimum feature size in the process technology used to produce it, said second silicon nitride strip intersecting said first silicon nitride strip at a location where it is desired to create an antifuse.

Claim 9

In an electrically programmable antifuse element including a dielectric layer between two conductive electrodes, one of said electrodes comprising an implanted region in a semiconductor substrate, a method for forming an antifuse aperture including the steps of: forming a thin silicon dioxide layer having a thickness of 1000 angstroms or less over said implanted region, forming a layer of negative resist over said thin silicon dioxide layer, forming a metal pad over said negative resist layer, said pad having an area larger than the desired area of said antifuse, isotropically etching said metal pad and said negative resist, to form a negative resist pad having an area equal to less than that of said metal pad, and removing said remaining portions of said metal layer and said negative resist.

Claim 10

In an electrically programmable antifuse element including a dielectric layer between two conductive electrodes, one of said electrodes comprising an implanted region in a semiconductor substrate, a method for forming an antifuse aperture including the steps of: forming a thin silicon dioxide layer having a thickness of 1000 angstroms or less over said implanted region, forming a layer of negative resist over said thin silicon dioxide layer, forming a metal pad over said negative resist layer, said pad having an area larger than the desired area of said antifuse, isotropically etching said metal pad and said negative resist, to form a negative resist pad having an area equal to less than that of said metal pad, and removing said remaining portions of said metal layer and said negative resist.

Claim 11

In an electrically programmable antifuse element including a dielectric layer between two conductive electrodes, one of said electrodes comprising an implanted region in a semiconductor substrate of a first conductivity type, a method for forming an antifuse aperture including the steps of: providing a masking layer on the surface of said silicon dioxide layer over the area in which it is desired to form said antifuse, forming spaced apart regions of a second conductivity type in said semiconductor substrate, using said masking layer as a mask, exposing said semiconductor substrate to an oxidizing atmosphere to form an intermediate silicon dioxide layer, removing said masking layer.

Claim 12

In an electrically programmable antifuse element including a dielectric layer between two conductive electrodes, one of said electrodes comprising an implanted region in a semiconductor substrate of a first conductivity type, a method for forming an antifuse aperture including the steps of: providing a masking layer on the surface of said silicon dioxide layer over the area in which it is desired to form said antifuse, forming spaced apart regions of a second conductivity type in said semiconductor substrate, using said masking layer as a mask, exposing said semiconductor substrate to an oxidizing atmosphere to form an intermediate silicon dioxide layer, removing said masking layer.