Signal delay circuit using charge pump circuit

Claim 2

A signal delay circuit comprising: variable delay means for delaying an input signal having a predetermined frequency by a time corresponding to a control signal; delay amount detecting means for detecting a signal delay amount of said delay means; and a charge pump circuit for receiving the input signal and a detection signal from said delay amount detecting means, generating a DC voltage corresponding to a pulse width ratio between the two signals, and feeding back the DC voltage to said variable delay means as the control signal.

Claim 3

A signal delay circuit comprising: first delay means, constituted by at least one delay stage having a signal delay time controlled on the basis of a control signal, for delaying an input signal having a predetermined frequency; a first logic circuit for detecting a signal delay amount of said first delay means; and a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with a current of an arbitrary multiple of a reference current on the basis of the input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, a power ratio between the charge and discharge currents being set to coincide with a reciprocal of a pulse width ratio between the input signal and the detection signal from said first logic circuit.

Claim 4

A signal delay circuit comprising: first delay means, constituted by at least one delay stage having a signal delay time controlled on the basis of a control signal, for delaying an input signal having a predetermined frequency; a first logic circuit for detecting a signal delay amount of said first delay means; and a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with a current of an arbitrary multiple of a reference current on the basis of the input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, a power ratio between the charge and discharge currents being set to coincide with a reciprocal of a pulse width ratio between the input signal and the detection signal from said first logic circuit.

Claim 5

A circuit according to claim 2, wherein a low-pass filter circuit is inserted between said charge pump circuit and said first delay means.

Claim 6

A circuit according to claim 2, wherein one delay stage of said first delay means comprises: an input node; a first transistor, connected at one terminal thereof to said input node, for receiving the control signal at a gate thereof; a first inverter having an input terminal connected to the other terminal of said first transistor; a second transistor having the same polarity as said first transistor, connected at one terminal thereof to an output terminal of said first inverter, for receiving the control signal at a gate thereof; a second inverter having an input terminal connected to the other terminal of said second transistor; an output node connected to an output terminal of said second inverter; and a third inverter having an input terminal connected to said output node.

Claim 7

A circuit according to claim 2, wherein one delay stage of said first delay means comprises: an input node; a first CMOS transmission gate connected at one terminal thereof to said input node and constituted by transistors having first and second polarities; a first inverter having an input terminal connected to the other terminal of said first transmission gate; a second CMOS transmission gate connected at one terminal thereof to an output terminal of said first inverter and constituted by transistors having the first and second polarities; a second inverter having an input terminal connected to the other terminal of said second CMOS transmission gate; an output node connected to an output terminal of said second inverter; and a third inverter having an input terminal connected to said output node, wherein said control signal is supplied to gates of said transistors having the first polarity of said first and second CMOS transmission gates, and a predetermined DC voltage is applied to gates of said transistors having the second polarity of said first and second CMOS transmission gates.

Claim 8

A circuit according to claim 2, wherein one delay stage of said variable first delay means comprises: an input node, an internal node, and an output node; first and second transistors of a first polarity, each having a source and a drain inserted in series between a first power source potential and said internal node, and having gates for receiving the control signal and a signal from said input node, respectively; a third transistor of a second polarity, having a source and a drain inserted between said internal node and a second power source potential, and a gate for receiving the signal from said input node; fourth and fifth transistors of the first polarity, each having a source and a drain inserted in series between the first power source potential and said output node, and having gates for receiving the control signal and the signal from said internal node, respectively; a sixth transistor of the second polarity, having a source and a drain between said output node and the second power source potential, and a gate for receiving the signal from said internal node; and a first inverter having an input terminal connected to said output node.

Claim 9

A circuit according to claim 2, wherein one delay stage of said first delay means comprises: an input node and an output node; a first inverter having an input terminal connected to said input node; first and second transistors of a first polarity, each having a source and a drain inserted in series between a first power source potential and said output node, and having gates for receiving the control signal and an output signal from said first inverter, respectively; and a third transistor of a second polarity, having a source and a drain inserted between said output node and a second power source potential, and a gate for receiving an output signal from said first inverter.

Claim 10

A circuit according to claim 2, wherein said charge pump circuit comprises: an output node for the DC voltage; first and second transistors of a first polarity, inserted in series between a first power source potential and said output node, and having gates for receiving a first predetermined reference voltage and an input signal having a predetermined frequency, respectively; third and fourth transistors of a second polarity, inserted in series between said output node and a second power source potential, and having gates for receiving an output signal from said first logic circuit and a second predetermined reference voltage, respectively; and a capacitor connected to said output node.

Claim 11

A circuit according to claim 2, wherein said first logic circuit receives an output signal from at least two delay stages of said first delay means and detects a signal delay amount of each delay stage.

Claim 12

A circuit according to claim 2, further comprising a reference voltage generator for generating the first and second reference voltages to be used to set the reference current value in said charge pump circuit.

Claim 13

A circuit according to claim 10, wherein said reference voltage generator comprises: first and second nodes for obtaining the first and second reference voltages, respectively; a first transistor of a first polarity having a source and a drain inserted between a first power source potential and said first node, and a gate connected to said first node; a second transistor of a second polarity having a source and a drain inserted between a second power source potential and said second node, and a gate connected to said second node; and a resistor connected between said first and second nodes.

Claim 14

A circuit according to claim 2, wherein in said charge pump circuit, the charge or discharge current value is arbitrarily controlled in accordance with an external control signal.

Claim 15

A circuit according to claim 12, wherein said charge pump circuit comprises: an output node for the DC voltage; first and second transistors of a first polarity, inserted in series between a first power source potential and said output node, and having gates for receiving a first predetermined reference voltage and the input signal having a predetermined frequency, respectively; third and fourth transistors of a second polarity, inserted in series between said output node and a second power source potential, and having gates for receiving a signal obtained by logically ANDing an output signal from said first logic circuit and an external first select signal and a second predetermined reference voltage, respectively; fifth and sixth transistors, inserted in series between said output node and the second power source potential, and having gates for receiving a signal obtained by logically ANDing the output signal from said first logic circuit and a second external select signal and a second predetermined reference voltage, respectively; and a capacitor connected to said output node.

Claim 16

A circuit according to claim 2, wherein a level converter for reducing a voltage change range of an output signal from said charge pump circuit is inserted between said charge pump circuit and said first delay means.

Claim 17

A circuit according to claim 14, wherein said level converter comprises: a first inverter for receiving an output signal from said charge pump circuit; and a second inverter of a source follower type for receiving an output signal from said first inverter.

Claim 18

A clock signal generator comprising: first delay means, constituted by at least one delay stage having a signal delay time controlled on the basis of a control signal, for delaying an input signal having a predetermined frequency; a first logic circuit for detecting a signal delay amount of said first delay means; a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with a current of an arbitrary multiple of a reference current on the basis of said input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, a power ratio between the charge and discharge currents being set to coincide with a reciprocal of a pulse width ratio between the input signal and the detection signal from said first logic circuit; and a second logic circuit for receiving a delayed output signal from at least said first delay means, and generating a clock signal having a frequency different from the frequency of the input signal on the basis of the delayed output signal.

Claim 19

A clock signal generator comprising: first delay means, constituted by at least one delay stage having a signal delay time controlled on the basis of a control signal, for delaying an input signal having a predetermined frequency; a first logic circuit for detecting a signal delay amount of said first delay means; a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with a current of an arbitrary multiple of a reference current on the basis of said input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, a power ratio between the charge and discharge currents being set to coincide with a reciprocal of a pulse width ratio between the input signal and the detection signal from said first logic circuit; and a second logic circuit for receiving a delayed output signal from at least said first delay means, and generating a clock signal having a frequency different from the frequency of the input signal on the basis of the delayed output signal.

Claim 20

A generator according to claim 16, wherein said second logic circuit receives the delayed output signal from said first delay means and the input signal, and generates a clock signal having a frequency higher than the frequency of the input signal.

Claim 21

A generator according to claim 16, wherein said second logic circuit generates a signal having a frequency which is an integer multiple of the frequency of the input signal as the clock signal.

Claim 22

A generator according to claim 18, wherein a low-pass filter circuit is inserted between said charge pump circuit and said first delay means.

Claim 23

A generator according to claim 18, wherein one delay stage of said first delay means comprises: an input node; a first transistor, connected at one terminal thereof to said input node, for receiving the control signal at a gate thereof; a first inverter having an input terminal connected to the other terminal of said first transistor; a second transistor having the same polarity as said first transistor, connected at one terminal thereof to an output terminal of said first inverter, for receiving the control signal at a gate thereof; a second inverter having an input terminal connected to the other terminal of said second transistor; an output node connected to an output terminal of said second inverter; and a third inverter having an input terminal connected to said output node.

Claim 24

A generator according to claim 18, wherein one delay stage of said first delay means comprises: an input node; a first CMOS transmission gate connected at one terminal thereof to said input node and constituted by transistors having first and second polarities; a first inverter having an input terminal connected to the other terminal of said first transmission gate; a second CMOS transmission gate connected at one terminal thereof to an output terminal of said first inverter and constituted by transistors having the first and second polarities; a second inverter having an input terminal connected to the other terminal of said second CMOS transmission gate; an output node connected to an output terminal of said second inverter; and a third inverter having an input terminal connected to said output node, wherein said control signal is supplied to gates of said transistors having the first polarity of said first and second CMOS transmission gates, and a predetermined DC voltage is applied to gates of said transistors having the second polarity of said first and second CMOS transmission gates.

Claim 25

A generator according to claim 18, wherein one delay stage of said first delay means comprises: an input node, an internal node, and an output node; first and second transistors of a first polarity, each having a source and a drain inserted in series between a first power source potential and said internal node, and having gates for receiving the control signal and a signal from said input node, respectively; a third transistor of a second polarity, having a source and a drain inserted between said internal node and a second power source potential, and a gate for receiving the signal from said input node; fourth and fifth transistors of the first polarity, each having a source and a drain inserted in series between the first power source potential and said output node, and having gates for receiving the control signal and the signal from said internal node, respectively; a sixth transistor of the second polarity, having a source and a drain between said output node and the second power source potential, and a gate for receiving the signal from said internal node; and a first inverter having an input terminal connected to said output node.

Claim 26

A generator according to claim 18, wherein one delay stage of said first delay means comprises: an input node and an output node; a first inverter having an input terminal connected to said input node; first and second transistors of a first polarity, each having a source and a drain inserted in series between a first power source potential and said output node, and having gates for receiving the control signal and an output signal from said first inverter, respectively; and a third transistor of a second polarity, having a source and a drain inserted between said output node and a second power source potential, and a gate for receiving an output signal from said first inverter.

Claim 27

A generator according to claim 18, wherein said charge pump circuit comprises: an output node for the DC voltage; first and second transistors of a first polarity, inserted in series between a first power source potential and said output node, and having gates for receiving a first predetermined reference voltage and an input signal having a predetermined frequency, respectively; third and fourth transistors of a second polarity, inserted in series between said output node and a second power source potential, and having gates for receiving an output signal from said first logic circuit and a second predetermined reference voltage, respectively; and a capacitor connected to said output node.

Claim 28

A generator according to claim 18, wherein said first logic circuit receives an output signal from at least two delay stages of said first delay means and detects a signal delay amount of each delay stage.

Claim 29

A generator according to claim 18, further comprising a reference voltage generator for generating the first and second reference voltages to be used to set the reference current value in said charge pump circuit.

Claim 30

A generator according to claim 26, wherein said reference voltage generator comprises: first and second nodes for obtaining the first and second reference voltages, respectively; a first transistor of a first polarity having a source and a drain inserted between a first power source potential and said first node, and a gate connected to said first node; a second transistor of a second polarity having a source and a drain inserted between a second power source potential and said second node, and a gate connected to said second node; and a resistor connected between said first and second nodes.

Claim 31

A generator according to claim 16, wherein said second logic circuit generates a multi-phase clock signal.

Claim 32

A generator according to claim 28, wherein a low-pass filter circuit is inserted between said charge pump circuit and said first delay means.

Claim 33

A generator according to claim 28, wherein one delay stage of said first delay means comprises: an input node; a first transistor, connected at one terminal thereof to said input node, for receiving the control signal at a gate thereof; a first inverter having an input terminal connected to the other terminal of said first transistor; a second transistor having the same polarity as said first transistor, connected at one terminal thereof to an output terminal of said first inverter, for receiving the control signal at a gate thereof; a second inverter having an input terminal connected to the other terminal of said second transistor; an output node connected to an output terminal of said second inverter; and a third inverter having an input terminal connected to said output node.

Claim 34

A generator according to claim 28, wherein one delay stage of said first delay means comprises: an input node; a first CMOS transmission gate connected at one terminal thereof to said input node and constituted by transistors having first and second polarities; a first inverter having an input terminal connected to the other terminal of said first transmission gate; a second CMOS transmission gate connected at one terminal thereof to an output terminal of said first inverter and constituted by transistors having the first and second polarities; a second inverter having an input terminal connected to the other terminal of said second CMOS transmission gate; an output node connected to an output terminal of said second inverter; and a third inverter having an input terminal connected to said output node, wherein said control signal is supplied to gates of said transistors having the first polarity of said first and second CMOS transmission gates, and a predetermined DC voltage is applied to gates of said transistors having the second polarity of said first and second CMOS transmission gates.

Claim 35

A generator according to claim 28, wherein one delay stage of said first delay means comprises: an input node, an internal node, and an output node; first and second transistors of a first polarity, each having a source and a drain inserted in series between a first power source potential and said internal node, and having gates for receiving the control signal and a signal from said input node, respectively; a third transistor of a second polarity, having a source and a drain inserted between said internal node and a second power source potential, and a gate for receiving the signal from said input node; fourth and fifth transistors of the first polarity, each having a source and a drain inserted in series between the first power source potential and said output node, and having gates for receiving the control signal and the signal from said internal node, respectively; a sixth transistor of the second polarity, having a source and a drain between said output node and the second power source potential, and a gate for receiving the signal from said internal node; and a first inverter having an input terminal connected to said output node.

Claim 36

A generator according to claim 28, wherein one delay stage of said first delay means comprises: an input node and an output node; a first inverter having an input terminal connected to said input node; first and second transistors of a first polarity, each having a source and a drain inserted in series between a first power source potential and said output node, and having gates for receiving the control signal and an output signal from said first inverter, respectively; and a third transistor of a second polarity, having a source and a drain inserted between said output node and a second power source potential, and a gate for receiving an output signal from said first inverter.

Claim 37

A generator according to claim 28, wherein said charge pump circuit comprises: an output node for the DC voltage; first and second transistors of a first polarity, inserted in series between a first power source potential and said output node, and having gates for receiving a first predetermined reference voltage and an input signal having a predetermined frequency, respectively; third and fourth transistors of a second polarity, inserted in series between said output node and a second power source potential, and having gates for receiving an output signal from said first logic circuit and a second predetermined reference voltage, respectively; and a capacitor connected to said output node.

Claim 38

A generator according to claim 28, wherein said first logic circuit receives an output signal from at least two delay stages of said first delay means and detects a signal delay amount of each delay stage.

Claim 39

A generator according to claim 28, further comprising a reference voltage generator for generating the first and second reference voltages to be used to set the reference current value in said charge pump circuit.

Claim 40

A generator according to claim 36, wherein said reference voltage generator comprises: first and second nodes for obtaining the first and second reference voltages, respectively; a first transistor of a first polarity having a source and a drain inserted between a first power source potential and said first node, and a gate connected to said first node; a second transistor of a second polarity having a source and a drain inserted between a second power source potential and said second node, and a gate connected to said second node; and a resistor connected between said first and second nodes.

Claim 41

A clock signal generator comprising: first delay means, constituted by at least one delay stage having a signal delay time controlled on the basis of a control signal, for delaying an input signal having a predetermined frequency; a first logic circuit for detecting a signal delay amount of said first delay means; a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with a current of an arbitrary multiple of a reference current on the basis of the input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, a power ratio between the charge and discharge currents being set to coincide with a reciprocal of a pulse width ratio between the input signal and a detection signal from said first logic circuit; a second logic circuit for receiving a delayed output signal from at least said first delay means, and generating a clock signal having a frequency different from the frequency of the input signal; and second delay means, constituted by at least one delay stage having the same arrangement as said delay stage of said first delay means and having a signal delay time controlled on the basis of a control signal generated by said charge pump circuit, for receiving an output signal from said second logic circuit.

Claim 42

A clock signal generator comprising: first delay means, constituted by at least one delay stage having a signal delay time controlled on the basis of a control signal, for delaying an input signal having a predetermined frequency; a first logic circuit for detecting a signal delay amount of said first delay means; a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with a current of an arbitrary multiple of a reference current on the basis of the input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, a power ratio between the charge and discharge currents being set to coincide with a reciprocal of a pulse width ratio between the input signal and a detection signal from said first logic circuit; a second logic circuit for receiving a delayed output signal from at least said first delay means, and generating a clock signal having a frequency different from the frequency of the input signal; and second delay means, constituted by at least one delay stage having the same arrangement as said delay stage of said first delay means and having a signal delay time controlled on the basis of a control signal generated by said charge pump circuit, for receiving an output signal from said second logic circuit.

Claim 43

A generator according to claim 38, wherein a low-pass filter circuit is inserted between said charge pump circuit and said first delay means.

Claim 44

A generator according to claim 38, wherein one delay stage of said first delay means comprises: an input node; a first transistor, connected at one terminal thereof to said input node, for receiving the control signal at a gate thereof; a first inverter having an input terminal connected to the other terminal of said first transistor; a second transistor having the same polarity as said first transistor, connected at one terminal thereof to an output terminal of said first inverter, for receiving the control signal at a gate thereof; a second inverter having an input terminal connected to the other terminal of said second transistor; an output node connected to an output terminal of said second inverter; and a third inverter having an input terminal connected to said output node.

Claim 45

A generator according to claim 38, wherein one delay stage of said first delay means comprises: an input node; a first CMOS transmission gate connected at one terminal thereof to said input node and constituted by transistors having first and second polarities; a first inverter having an input terminal connected to the other terminal of said first transmission gate; a second CMOS transmission gate connected at one terminal thereof to an output terminal of said first inverter and constituted by transistors having the first and second polarities; a second inverter having an input terminal connected to the other terminal of said second CMOS transmission gate; an output node connected to an output terminal of said second inverter; and a third inverter having an input terminal connected to said output node, wherein said control signal is supplied to gates of said transistors having the first polarity of said first and second CMOS transmission gates, and a predetermined DC voltage is applied to gates of said transistors having the second polarity of said first and second CMOS transmission gates.

Claim 46

A generator according to claim 38, wherein one delay stage of said first delay means comprises: an input node, an internal node, and an output node; first and second transistors of a first polarity, each having a source and a drain inserted in series between a first power source potential and said internal node, and having gates for receiving the control signal and a signal from said input node, respectively; a third transistor of a second polarity, having a source and a drain inserted between said internal node and a second power source potential, and a gate for receiving the signal from said input node; fourth and fifth transistors of the first polarity, each having a source and a drain inserted in series between the first power source potential and said output node, and having gates for receiving the control signal and the signal from said internal node, respectively; a sixth transistor of the second polarity, having a source and a drain between said output node and the second power source potential, and a gate for receiving the signal from said internal node; and a first inverter having an input terminal connected to said output node.

Claim 47

A generator according to claim 38, wherein one delay stage of said first delay means comprises: an input node and an output node; a first inverter having an input terminal connected to said input node; first and second transistors of a first polarity, each having a source and a drain inserted in series between a first power source potential and said output node, and having gates for receiving the control signal and an output signal from said first inverter, respectively; and a third transistor of a second polarity, having a source and a drain inserted between said output node and a second power source potential, and a gate for receiving an output signal from said first inverter.

Claim 48

A generator according to claim 38, wherein said charge pump circuit comprises: an output node for the DC voltage; first and second transistors of a first polarity, inserted in series between a first power source potential and said output node, and having gates for receiving a first predetermined reference voltage and an input signal having a predetermined frequency, respectively; third and fourth transistors of a second polarity, inserted in series between said output node and a second power source potential, and having gates for receiving an output signal from said first logic circuit and a second predetermined reference voltage (Vn), respectively; and a capacitor connected to said output node.

Claim 49

A generator according to claim 38, wherein said first logic circuit receives an output signal from at least two delay stages of said first delay means and detects a signal delay amount of each delay stage.

Claim 50

A generator according to claim 38, further comprising a reference voltage generator for generating the first and second reference voltages to be used to set the reference current value in said charge pump circuit.

Claim 51

A generator according to claim 46, wherein said reference voltage generator comprises: first and second nodes for obtaining the first and second reference voltages, respectively; a first transistor of a first polarity having a source and a drain inserted between a first power source potential and said first node, and a gate connected to said first node; a second transistor of a second polarity having a source and a drain inserted between a second power source potential and said second node, and a gate connected to said second node; and a resistor connected between said first and second nodes.

Claim 52

A clock signal generator comprising: first delay means, constituted by at least one delay stage having a signal delay time controlled on the basis of a control signal, for delaying an input signal having a predetermined frequency; a first logic circuit for detecting a signal delay amount of said first delay means; a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with a current of an arbitrary multiple of a reference current on the basis of the input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, a power ratio between the charge and discharge currents being set to coincide with a reciprocal of a pulse width ratio between the input signal and the detection signal from said first logic circuit; second delay means constituted by at least one delay stage having the same arrangement as said delay stage in said first delay means and having a signal delay time controlled on the basis of the control signal generated by said charge pump circuit; and feedback means for feeding back an output signal from said second delay means to an input side thereof.

Claim 53

A clock signal generator comprising: first delay means, constituted by at least one delay stage having a signal delay time controlled on the basis of a control signal, for delaying an input signal having a predetermined frequency; a first logic circuit for detecting a signal delay amount of said first delay means; a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with a current of an arbitrary multiple of a reference current on the basis of the input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, a power ratio between the charge and discharge currents being set to coincide with a reciprocal of a pulse width ratio between the input signal and the detection signal from said first logic circuit; second delay means constituted by at least one delay stage having the same arrangement as said delay stage in said first delay means and having a signal delay time controlled on the basis of the control signal generated by said charge pump circuit; and feedback means for feeding back an output signal from said second delay means to an input side thereof.

Claim 54

A generator according to claim 48, wherein a low-pass filter circuit is inserted between said charge pump circuit and said first delay means.

Claim 55

A generator according to claim 48, wherein one delay stage of said first delay means comprises: an input node; a first transistor, connected at one terminal thereof to said input node, for receiving the control signal at a gate thereof; a first inverter having an input terminal connected to the other terminal of said first transistor; a second transistor having the same polarity as said first transistor, connected at one terminal thereof to an output terminal of said first inverter, for receiving the control signal at a gate thereof; a second inverter having an input terminal connected to the other terminal of said second transistor; an output node connected to an output terminal of said second inverter; and a third inverter having an input terminal connected to said output node.

Claim 56

A generator according to claim 48, wherein one delay stage of said first delay means comprises: an input node; a first CMOS transmission gate connected at one terminal thereof to said input node and constituted by transistors having first and second polarities; a first inverter having an input terminal connected to the other terminal of said first transmission gate; a second CMOS transmission gate connected at one terminal thereof to an output terminal of said first inverter and constituted by transistors having the first and second polarities; a second inverter having an input terminal connected to the other terminal of said second CMOS transmission gate; an output node connected to an output terminal of said second inverter; and a third inverter having an input terminal connected to said output node, wherein said control signal is supplied to gates of said transistors having the first polarity of said first and second CMOS transmission gates, and a predetermined DC voltage is applied to gates of said transistors having the second polarity of said first and second CMOS transmission gates.

Claim 57

A generator according to claim 48, wherein one delay stage of said first delay means comprises: an input node, an internal node, and an output node; first and second transistors of a first polarity, each having a source and a drain inserted in series between a first power source potential and said internal node, and having gates for receiving the control signal and a signal from said input node, respectively; a third transistor of a second polarity, having a source and a drain inserted between said internal node and a second power source potential, and a gate for receiving the signal from said input node; fourth and fifth transistors of the first polarity, each having a source and a drain inserted in series between the first power source potential and said output node, and having gates for receiving the control signal and the signal from said internal node, respectively; a sixth transistor of the second polarity, having a source and a drain between said output node and the second power source potential, and a gate for receiving the signal from said internal node; and a first inverter having an input terminal connected to said output node.

Claim 58

A generator according to claim 48, wherein one delay stage of said first delay means comprises: an input node and an output node; a first inverter having an input terminal connected to said input node; first and second transistors of a first polarity, each having a source and a drain inserted in series between a first power source potential and said output node, and having gates for receiving the control signal and an output signal from said first inverter, respectively; and a third transistor of a second polarity, having a source and a drain inserted between said output node and a second power source potential, and a gate for receiving an output signal from said first inverter.

Claim 59

A generator according to claim 48, wherein said charge pump circuit comprises: an output node for the DC voltage; first and second transistors of a first polarity, inserted in series between a first power source potential and said output node, and having gates for receiving a first predetermined reference voltage and an input signal having a predetermined frequency, respectively; third and fourth transistors of a second polarity, inserted in series between said output node and a second power source potential, and having gates for receiving an output signal from said first logic circuit and a second predetermined reference voltage, respectively; and a capacitor connected to said output node.

Claim 60

A generator according to claim 48, wherein said first logic circuit receives an output signal from at least two delay stages of said first delay means and detects a signal delay amount of each delay stage.

Claim 61

A generator according to claim 48, further comprising a reference voltage generator for generating the first and second reference voltages to be used to set the reference current value in said charge pump circuit.

Claim 62

A generator according to claim 56, wherein said reference voltage generator comprises: first and second nodes for obtaining the first and second reference voltages, respectively; a first transistor of a first polarity having a source and a drain inserted between a first power source potential and said first node, and a gate connected to said first node; a second transistor of a second polarity having a source and a drain inserted between a second power source potential and said second node, and a gate connected to said second node; and a resistor connected between said first and second nodes.

Claim 63

A clock signal generator comprising: first delay means, including at least one stage of cascade-connected delay stages, each of said delay stages being constituted by an input node, a first CMOS transmission gate connected at one terminal thereof to said input node and having transistors of first and second polarities, said transistor of the first polarity having a gate for receiving a control signal, and said transistor of the second polarity having a gate for receiving a reference voltage signal, a first inverter having an input terminal connected to the other terminal of said first transmission gate, a second CMOS transmission gate connected at one terminal thereof to an output terminal of said first inverter and having transistors of the first and second polarities, the control signal being supplied to a gate of said transistor of the first polarity, and the reference voltage signal being supplied to a gate of said transistor of the second polarity, a second inverter having an input terminal connected to the other terminal of said second CMOS transmission gate, an output node connected to an output terminal of said second inverter, and a third inverter having an input terminal connected to said output node, said first delay means being connected to delay an input signal having a predetermined frequency; a first logic circuit for detecting a signal delay amount of said first delay means; a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with a current of an arbitrary multiple of a reference current on the basis of the input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, a power ratio between the charge and discharge currents being set to coincide with a reciprocal of a pulse width ratio between the input signal and a detection signal of said first logic circuit; second delay means, including at least one stage of cascade-connected delay stages, each of said delay stages being constituted by an input node, a third CMOS transmission gate connected at one terminal thereof to said input node and having transistors of the first and second polarities, said transistor of the first polarity having a gate for receiving a control signal generated by said charge pump circuit, and said transistor of the second polarity having a gate for receiving an oscillation frequency control voltage signal, a fourth inverter having an input terminal connected to the other terminal of said third transmission gate, a fourth CMOS transmission gate connected at one terminal thereof to an output terminal of said fourth inverter and having transistors of the first and second polarities, the control signal generated by said charge pump circuit being supplied to a gate of said transistor of the first polarity, and the oscillation frequency control voltage signal being supplied to a gate of said transistor of the second polarity, a fifth inverter having an input terminal connected to the other terminal of said fourth CMOS transmission gate, and an output node connected to an output terminal of said fifth inverter; and feedback means for feeding back an output signal from said second delay means to an input side thereof.

Claim 64

A clock signal generator comprising: first delay means, including at least one stage of cascade-connected delay stages, each of said delay stages being constituted by an input node, a first CMOS transmission gate connected at one terminal thereof to said input node and having transistors of first and second polarities, said transistor of the first polarity having a gate for receiving a control signal, and said transistor of the second polarity having a gate for receiving a reference voltage signal, a first inverter having an input terminal connected to the other terminal of said first transmission gate, a second CMOS transmission gate connected at one terminal thereof to an output terminal of said first inverter and having transistors of the first and second polarities, the control signal being supplied to a gate of said transistor of the first polarity, and the reference voltage signal being supplied to a gate of said transistor of the second polarity, a second inverter having an input terminal connected to the other terminal of said second CMOS transmission gate, an output node connected to an output terminal of said second inverter, and a third inverter having an input terminal connected to said output node, said first delay means being connected to delay an input signal having a predetermined frequency; a first logic circuit for detecting a signal delay amount of said first delay means; a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with a current of an arbitrary multiple of a reference current on the basis of the input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, a power ratio between the charge and discharge currents being set to coincide with a reciprocal of a pulse width ratio between the input signal and a detection signal of said first logic circuit; second delay means, including at least one stage of cascade-connected delay stages, each of said delay stages being constituted by an input node, a third CMOS transmission gate connected at one terminal thereof to said input node and having transistors of the first and second polarities, said transistor of the first polarity having a gate for receiving a control signal generated by said charge pump circuit, and said transistor of the second polarity having a gate for receiving an oscillation frequency control voltage signal, a fourth inverter having an input terminal connected to the other terminal of said third transmission gate, a fourth CMOS transmission gate connected at one terminal thereof to an output terminal of said fourth inverter and having transistors of the first and second polarities, the control signal generated by said charge pump circuit being supplied to a gate of said transistor of the first polarity, and the oscillation frequency control voltage signal being supplied to a gate of said transistor of the second polarity, a fifth inverter having an input terminal connected to the other terminal of said fourth CMOS transmission gate, and an output node connected to an output terminal of said fifth inverter; and feedback means for feeding back an output signal from said second delay means to an input side thereof.

Claim 65

A generator according to claim 58, wherein said feedback means is constituted by an inverter.

Claim 66

A generator according to claim 58, wherein a low-pass filter circuit is inserted between said charge pump circuit and said first delay means.

Claim 67

A generator according to claim 58, wherein said charge pump circuit comprises: an output node for the DC voltage; first and second transistors of a first polarity, inserted in series between a first power source potential and said output node, and having gates for receiving a first predetermined reference voltage and an input signal having a predetermined frequency, respectively; third and fourth transistors of a second polarity, inserted in series between said output node and a second power source potential, and having gates for receiving an output signal from said first logic circuit and a second predetermined reference voltage, respectively; and a capacitor connected to said output node.

Claim 68

A generator according to claim 58, wherein said first logic circuit receives an output signal from at least two delay stages of said first delay means and detects a signal delay amount of each delay stage.

Claim 69

A generator according to claim 58, further comprising a reference voltage generator for generating the first and second reference voltages to be used to set the reference current value in said charge pump circuit.

Claim 70

A generator according to claim 63, wherein said reference voltage generator comprises: first and second nodes for obtaining the first and second reference voltages, respectively; a first transistor of a first polarity having a source and a drain inserted between a first power source potential and said first node, and a gate connected to said first node; a second transistor of a second polarity having a source and a drain inserted between a second power source potential and said second node, and a gate connected to said second node; and a resistor connected between said first and second nodes.