Semiconductor integrated circuit device and a method of producing the same

Claim 1

A method of producing a semiconductor device having a memory cell array, said memory cell array having a plurality of MISFET's that are connected in series and form cell rows, comprising the steps of: introducing impurities into a surface of a semiconductor material having a first type of conductivity, said impurities having a second type of conductivity that is opposite to said first type of conductivity; forming a plurality of first conductive layers maintaining an equal distance on the surface of said semiconductor material; forming a plurality of second conductive layers among said plurality of first conductive layers on the surface of said semiconductor material, in such a manner that said second conductive layers are partly overlapped on said first conductive layers, said first and second conductive layers constituting gate electrodes of said MISFET's that are connected in series, said MISFET's forming said cell rows; forming a masking layer having openings at positions corresponding to particular ones of the plurality of first and second conductive layers; and selectively introducing impurities of the first conductivity type into the openings utilizing said masking layer, wherein said impurities of the first conductivity type are introduced into the channel-forming regions of said MISFET's.

Claim 2

A method of producing a semiconductor device having a memory cell array, said memory cell array having a plurality of MISFET's that are connected in series and form cell rows, comprising the steps of: introducing impurities into a surface of a semiconductor material having a first type of conductivity, said impurities having a second type of conductivity that is opposite to said first type of conductivity; forming a plurality of first conductive layers maintaining an equal distance on the surface of said semiconductor material; forming a plurality of second conductive layers among said plurality of first conductive layers on the surface of said semiconductor material, in such a manner that said second conductive layers are partly overlapped on said first conductive layers, said first and second conductive layers constituting gate electrodes of said MISFET's that are connected in series, said MISFET's forming said cell rows; forming a masking layer having openings at positions corresponding to particular ones of the plurality of first and second conductive layers; and selectively introducing impurities of the first conductivity type into the openings utilizing said masking layer, wherein said impurities of the first conductivity type are introduced into the channel-forming regions of said MISFET's.

Claim 11

A method of producing a semiconductor device having a mask ROM, comprising the steps of: introducing impurities into a surface of a semiconductor material having p conductivity type, said impurities having n conductivity type; forming a plurality of first conductive layers maintaining an equal distance on the surface of said semiconductor material; forming a plurality of second conductive layers among said plurality of first conductive layers on the surface of said semiconductor material, in such a manner that said second conductive layers are partly overlapped on said first conductive layers, said second conductive layers having a thickness substantially the same as the thickness of said first conductive layers, said first and second conductive layers constituting gate electrodes of MISFET's that are connected in series, said MISFET's constituting memory cells of said mask ROM; forming a masking layer having openings at positions corresponding to particular ones of the plurality of first conductive and second conductive layers; and selectively introducing impurities of p conductivity type, for writing data, into the openings utilizing said masking layer, wherein said impurities of p conductivity type are introduced into the channel-forming regions of said MISFET's, and wherein portions where said first conductive layer and second conductive layer are overlapped act as a mask in the selective introduction of p conductivity type impurities.

Claim 12

A method of producing a semiconductor device having a mask ROM, comprising the steps of: introducing impurities into a surface of a semiconductor material having p conductivity type, said impurities having n conductivity type; forming a plurality of first conductive layers maintaining an equal distance on the surface of said semiconductor material; forming a plurality of second conductive layers among said plurality of first conductive layers on the surface of said semiconductor material, in such a manner that said second conductive layers are partly overlapped on said first conductive layers, said second conductive layers having a thickness substantially the same as the thickness of said first conductive layers, said first and second conductive layers constituting gate electrodes of MISFET's that are connected in series, said MISFET's constituting memory cells of said mask ROM; forming a masking layer having openings at positions corresponding to particular ones of the plurality of first conductive and second conductive layers; and selectively introducing impurities of p conductivity type, for writing data, into the openings utilizing said masking layer, wherein said impurities of p conductivity type are introduced into the channel-forming regions of said MISFET's, and wherein portions where said first conductive layer and second conductive layer are overlapped act as a mask in the selective introduction of p conductivity type impurities.

Claim 13

A method of producing a semiconductor memory device having a memory cell array, said memory cell array having cell rows, comprising the steps of: introducing impurities into a surface of a semiconductor material having a first type of conductivity, said impurities having a second type of conductivity that is opposite to said first type of conductivity; forming a plurality of first conductive layers maintaining an equal distance on the surface of said semiconductor material; forming a plurality of second conductive layers among said plurality of first conductive layers on the surface of said semiconductor material, in such a manner that said second conductive layers are partly overlapped on said first conductive layers, said second conductive layers having a thickness substantially the same as a thickness of said first conductive layers, said first and second conductive layers constituting gate electrodes of MISFET's that are connected in series, said MISFET's forming said cell rows; forming a first insulating film on said semiconductor material and on the first and second conductive layers; selectively forming a third conductive layer on said first insulating film; forming a second insulating film on said first insulating film and on said third conductive layer; forming a masking layer on said second insulating film; selectively removing said masking layer using said second insulating film as an etching-preventing film, so as to form openings therein; and selectively introducing impurities of the first type of conductivity into the openings utilizing said masking layer, wherein said impurities of the first conductivity type are introduced into the channel-forming regions of said MISFET's, and wherein portions where said first conductive layer and second conductive layer are overlapped act as a mask in the selective introduction of impurities of the firs type of conductivity.

Claim 14

A method of producing a semiconductor memory device having a memory cell array, said memory cell array having cell rows, comprising the steps of: introducing impurities into a surface of a semiconductor material having a first type of conductivity, said impurities having a second type of conductivity that is opposite to said first type of conductivity; forming a plurality of first conductive layers maintaining an equal distance on the surface of said semiconductor material; forming a plurality of second conductive layers among said plurality of first conductive layers on the surface of said semiconductor material, in such a manner that said second conductive layers are partly overlapped on said first conductive layers, said second conductive layers having a thickness substantially the same as a thickness of said first conductive layers, said first and second conductive layers constituting gate electrodes of MISFET's that are connected in series, said MISFET's forming said cell rows; forming a first insulating film on said semiconductor material and on the first and second conductive layers; selectively forming a third conductive layer on said first insulating film; forming a second insulating film on said first insulating film and on said third conductive layer; forming a masking layer on said second insulating film; selectively removing said masking layer using said second insulating film as an etching-preventing film, so as to form openings therein; and selectively introducing impurities of the first type of conductivity into the openings utilizing said masking layer, wherein said impurities of the first conductivity type are introduced into the channel-forming regions of said MISFET's, and wherein portions where said first conductive layer and second conductive layer are overlapped act as a mask in the selective introduction of impurities of the firs type of conductivity.