Clocked logic circuitry preventing double driving on shared data bus

Claim 2

In a digital computer system where multiple digital data sources can be connected to transmit data onto a common system bus made of "k" bit lines, a bus access and double drive prevention system comprising: (a) a plurality of digital data source units each of which includes: (a1) plurality of driver means for driving data onto said system bus, each said driver means including: (a1a) a set of "k" driver units for each set of bus bit lines for each said data source units; (a2) a plurality of means for enabling system bus access to only one of said set of "k" driver units during any given clock cycle, wherein each said means includes: (a2a) control gating logic means for enabling a selected one of said plurality of digital data source units while disabling all other digital data source units, and wherein each said control gating logic means includes: (a2ai) an AND gate which is connected to enable or disable its associated set of driver units; (a2aii) a flip-flop circuit connected as an input to said AND gate; (a2aiii) clock means connected to transmit clock signals to said flip-flop circuit.

Claim 3

In a digital computer network using a plurality of data source for transmitting data over a shared system bus to a selected one of a plurality of receiver units, a bus access and double drive prevention system comprising: (a) a plurality of data source modules connected to said system bus wherein each of said modules includes: (a1) a digital data source unit for holding digital data to be transmitted; (a2) a set of driver units for moving digital data from one of said data source modules onto said system bus, said set of driver units providing one driver unit for each bit line of said bus; (a3) gating logic means for enabling one of said data source modules to transmit data onto said system bus one clock cycle after all other data source modules have been disabled from transmitting data onto said system bus, said gating logic means including: (a3a) a control logic unit connected to enable/disable said set of driver units wherein said control logic unit includes: (a3ai) flip-flop circuit means for clocking an associated AND gate at a clock rate determined by a clocking means; (a3aii) said clocking means connected to drive a clock signal to each one of said flip-flop circuit means; (a3aiii) said associated AND gate including input instruction signals for enabling/disabling its associated set of driver units to permit/inhibit data transmission onto said system bus.

Claim 4

In a digital computer network using a plurality of data source for transmitting data over a shared system bus to a selected one of a plurality of receiver units, a bus access and double drive prevention system comprising: (a) a plurality of data source modules connected to said system bus wherein each of said modules includes: (a1) a digital data source unit for holding digital data to be transmitted; (a2) a set of driver units for moving digital data from one of said data source modules onto said system bus, said set of driver units providing one driver unit for each bit line of said bus; (a3) gating logic means for enabling one of said data source modules to transmit data onto said system bus one clock cycle after all other data source modules have been disabled from transmitting data onto said system bus, said gating logic means including: (a3a) a control logic unit connected to enable/disable said set of driver units wherein said control logic unit includes: (a3ai) flip-flop circuit means for clocking an associated AND gate at a clock rate determined by a clocking means; (a3aii) said clocking means connected to drive a clock signal to each one of said flip-flop circuit means; (a3aiii) said associated AND gate including input instruction signals for enabling/disabling its associated set of driver units to permit/inhibit data transmission onto said system bus.