Patent US5095228A successfully refreshed from Google Patents.
US5095228A
Expired / Lapsed
US
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Circuits for preventing breakdown of low-voltage device inputs during high voltage antifuse programming
Assignee: Microsemi SoC Corp
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Filing: 1991-04-19
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Granted: 1992-03-10
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Expires: 2011-04-19
Abstract
Abstract A circuit for isolating a first low-voltage circuit mode from a second circuit node which carries high programming voltages during programming of user-programmable interconnect elements includes a novel two input NAND gate having one input structure configured from high voltage devices connected to the second circuit node. The other input of the NAND gate is a control input for the isolation device and is connected to a low-voltage logic signal which is high when the signal from the high programming voltage node is to be passed through to the low-voltage node and low when the low-voltage node is to be isolated from the high programming voltage node. The output of the NAND gate is connected to the first low-voltage circuit node.
Inventors
- 👤 Douglas C. Galbraith
- 👤 Jonathan W. Greene
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:55
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/10; H03K17/102; G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; H03K19/00; H03K19/003; H03K19/00315
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
135 words
In a user-configurable integrated circuit employing low-voltage circuit elements which may be interconnected by user-programmable interconnection elements which may be programmed by a programming voltage having a magnitude larger than the voltage which can be withstood by said low-voltage circuit elements, an isolation circuit for protecting low-voltage circuit nodes to which said low-voltage circuit elements are connected from destruction by application of said programming voltage during programming of said integrated circuit, comprising a NAND gate, said NAND gate having a first input connected to a circuit node upon which said programming voltage may appear, said first input configured to withstand said programming voltage, a second input connected to a control logic signal at voltage levels compatible with operation of said low-voltage circuits, and an output connected to at least one of said low-voltage circuit elements.
Claim 2
Dependent Claim
135 words
In a user-configurable integrated circuit employing low-voltage circuit elements which may be interconnected by user-programmable interconnection elements which may be programmed by a programming voltage having a magnitude larger than the voltage which can be withstood by said low-voltage circuit elements, an isolation circuit for protecting low-voltage circuit nodes to which said low-voltage circuit elements are connected from destruction by application of said programming voltage during programming of said integrated circuit, comprising a NAND gate, said NAND gate having a first input connected to a circuit node upon which said programming voltage may appear, said first input configured to withstand said programming voltage, a second input connected to a control logic signal at voltage levels compatible with operation of said low-voltage circuits, and an output connected to at least one of said low-voltage circuit elements.
Claim 3
Dependent Claim
172 words
In a user-configurable integrated circuit employing low-voltage circuit elements which may be interconnected by user-programmable interconnection elements which may be programmed by a programming voltage having a magnitude larger than the voltage which can be withstood by said low-voltage circuit elements, an isolation circuit for protecting a first, low-voltage, circuit node to which said low-voltage circuit elements is connected from destruction by application of said programming voltage to a second, high voltage, circuit node which may carry high voltage during programming of said integrated circuit, comprising: a control node; a P-channel MOS transistor having a gate connected to second circuit node, a source connected to a first voltage source for said low-voltage circuit elements, and a drain connected to said first circuit node, said P-channel MOS transistor fabricated to withstand said programming voltage; an N-channel MOS transistor having a gate connected to second circuit node, and a drain connected to said first circuit node, and a source connected to said control node, said N-channel MOS transistor fabricated to withstand said programming voltage.
Claim 4
Dependent Claim
172 words
In a user-configurable integrated circuit employing low-voltage circuit elements which may be interconnected by user-programmable interconnection elements which may be programmed by a programming voltage having a magnitude larger than the voltage which can be withstood by said low-voltage circuit elements, an isolation circuit for protecting a first, low-voltage, circuit node to which said low-voltage circuit elements is connected from destruction by application of said programming voltage to a second, high voltage, circuit node which may carry high voltage during programming of said integrated circuit, comprising: a control node; a P-channel MOS transistor having a gate connected to second circuit node, a source connected to a first voltage source for said low-voltage circuit elements, and a drain connected to said first circuit node, said P-channel MOS transistor fabricated to withstand said programming voltage; an N-channel MOS transistor having a gate connected to second circuit node, and a drain connected to said first circuit node, and a source connected to said control node, said N-channel MOS transistor fabricated to withstand said programming voltage.
Claim 5
Dependent Claim
253 words
In a user-configurable integrated circuit employing low-voltage circuit elements which may be interconnected by user-programmable interconnection elements which may be programmed by a programming voltage having a magnitude larger than the voltage which can be withstood by said low-voltage circuit elements, an isolation circuit for protecting a first, low-voltage, circuit node to which said low-voltage circuit elements is connected from destruction by application of said programming voltage to a second, high voltage, circuit node which may carry high voltage during programming of said integrated circuit, comprising: a control node; a first P-channel MOS transistor having a gate connected to second circuit node, a source connected to a first voltage source for said low-voltage circuit elements, and a drain connected to said first circuit node, said first P-channel MOS transistor fabricated to withstand said programming voltage; a first N-channel MOS transistor having a gate connected to second circuit node, and a drain connected to said first circuit node, and a source, said first N-channel MOS transistor fabricated to withstand said programming voltage; a second N-channel MOS transistor having a drain connected to said source of said first N-channel MOS transistor, a source connected to a second voltage source for said low-voltage circuit elements, said second voltage source at a lower potential than said first voltage source, and a gate connected to said control node; a second P-channel MOS transistor having a source connected to said first voltage source, a drain connected to said first circuit node, and a gate connected to said control node.
Claim 6
Dependent Claim
253 words
In a user-configurable integrated circuit employing low-voltage circuit elements which may be interconnected by user-programmable interconnection elements which may be programmed by a programming voltage having a magnitude larger than the voltage which can be withstood by said low-voltage circuit elements, an isolation circuit for protecting a first, low-voltage, circuit node to which said low-voltage circuit elements is connected from destruction by application of said programming voltage to a second, high voltage, circuit node which may carry high voltage during programming of said integrated circuit, comprising: a control node; a first P-channel MOS transistor having a gate connected to second circuit node, a source connected to a first voltage source for said low-voltage circuit elements, and a drain connected to said first circuit node, said first P-channel MOS transistor fabricated to withstand said programming voltage; a first N-channel MOS transistor having a gate connected to second circuit node, and a drain connected to said first circuit node, and a source, said first N-channel MOS transistor fabricated to withstand said programming voltage; a second N-channel MOS transistor having a drain connected to said source of said first N-channel MOS transistor, a source connected to a second voltage source for said low-voltage circuit elements, said second voltage source at a lower potential than said first voltage source, and a gate connected to said control node; a second P-channel MOS transistor having a source connected to said first voltage source, a drain connected to said first circuit node, and a gate connected to said control node.
Claim 7
Dependent Claim
221 words
In a user-configurable integrated circuit employing low-voltage circuit elements which may be interconnected by user-programmable interconnection elements which may be programmed by a programming voltage having a magnitude larger than the voltage which can be withstood by said low-voltage circuit elements, an isolation circuit for protecting a first, low-voltage, circuit node to which said low-voltage circuit elements is connected from destruction by application of said programming voltage to a second, high voltage, circuit node which may carry high voltage during programming of said integrated circuit, comprising: a control node; a first P-channel MOS transistor having a gate connected to second circuit node, a source connected to a first voltage source for said low-voltage circuit elements, and a drain connected to said first circuit node, said first P-channel MOS transistor fabricated to withstand said programming voltage; an N-channel MOS transistor having a gate connected to second circuit node, and a drain connected to said first circuit node, and a source, said N-channel MOS transistor fabricated to withstand said programming voltage; a second P-channel MOS transistor having a source connected to said first voltage source, a drain connected to said first circuit node, and a gate connected to said control node; in inverter having an input connected to said control node and an output connected to said source of said N-channel MOS transistor.
Claim 8
Dependent Claim
221 words
In a user-configurable integrated circuit employing low-voltage circuit elements which may be interconnected by user-programmable interconnection elements which may be programmed by a programming voltage having a magnitude larger than the voltage which can be withstood by said low-voltage circuit elements, an isolation circuit for protecting a first, low-voltage, circuit node to which said low-voltage circuit elements is connected from destruction by application of said programming voltage to a second, high voltage, circuit node which may carry high voltage during programming of said integrated circuit, comprising: a control node; a first P-channel MOS transistor having a gate connected to second circuit node, a source connected to a first voltage source for said low-voltage circuit elements, and a drain connected to said first circuit node, said first P-channel MOS transistor fabricated to withstand said programming voltage; an N-channel MOS transistor having a gate connected to second circuit node, and a drain connected to said first circuit node, and a source, said N-channel MOS transistor fabricated to withstand said programming voltage; a second P-channel MOS transistor having a source connected to said first voltage source, a drain connected to said first circuit node, and a gate connected to said control node; in inverter having an input connected to said control node and an output connected to said source of said N-channel MOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-10 | 1995-09-09 | 1996-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-10 | 1999-09-09 | 2000-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-10 | 2003-09-09 | 2004-03-10 | $7700.00 | Window Closed / Lapsed |