US5148530A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for reexecuting instruction by altering high bits of instruction address based upon result of a subtraction operation with stored low bits
Assignee: Bull HN Information Systems Inc
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Filing: 1989-09-06
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Granted: 1992-09-15
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Expires: 2009-09-06
Abstract
Abstract In a data processing system using a virtual memory adressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value.
Inventors
- 👤 Thomas F. Joyce
- 👤 Richard P. Kelly
- 👤 Jian-Kuo Shen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:01
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/141; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3005; G06F9/38; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
162 words
A method of initializing an instruction in a data processing system if execution of the instruction is interrupted following modification of the instruction address by a first predetermined amount and storage of the modified address in a first register, characterized by: a) storing a lower order portion of said instruction address in a second register concurrently with said modification; b) following said interruption, retrieving said lower order portion from said second register and the lower order portion of the modified instruction address from said first register and performing a subtraction operation on said lower order portions; c) performing a test to determine whether a carry occurred as a result of said subtraction operation; d) modifying by a second predetermined amount the higher order portion of said modified instruction address if said test determines a particular result; and e) concatentating the higher order portion of said modified instruction address and the lower order portion of the instruction address held in said second register.
Claim 2
Independent Claim
162 words
A method of initializing an instruction in a data processing system if execution of the instruction is interrupted following modification of the instruction address by a first predetermined amount and storage of the modified address in a first register, characterized by: a) storing a lower order portion of said instruction address in a second register concurrently with said modification; b) following said interruption, retrieving said lower order portion from said second register and the lower order portion of the modified instruction address from said first register and performing a subtraction operation on said lower order portions; c) performing a test to determine whether a carry occurred as a result of said subtraction operation; d) modifying by a second predetermined amount the higher order portion of said modified instruction address if said test determines a particular result; and e) concatentating the higher order portion of said modified instruction address and the lower order portion of the instruction address held in said second register.
Claim 3
Dependent Claim
66 words
The method of claim 1, wherein said instruction address is represented by a number in binary digital form and said modification of said instruction address is the incrementation thereof, and further characterized in that: said lower order portions comprise the three lower order bits of the respective instruction addresses, and said higher order portion is modified in step (d) by subtracting therefrom the value hexadecimal 8.
Claim 4
Dependent Claim
66 words
The method of claim 1, wherein said instruction address is represented by a number in binary digital form and said modification of said instruction address is the decrementation thereof, and further characterized in that: said lower order portions comprise the three lower order bits of the respective instruction addresses, and said higher order portion is modified in step (d) by adding thereto the value hexadecimal 8.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-15 | 1996-03-16 | 1996-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-15 | 2000-03-16 | 2000-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-15 | 2004-03-16 | 2004-09-15 | $7700.00 | Window Closed / Lapsed |