Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
219 words
A sense amplifier for a non-volatile semiconductor storage device having a plurality of memory cells in a memory cell array, said sense amplifier comprising: a true and a complementary input terminal (TI, TII) for receiving a true and a complementary input signal (SI, SII) from said memory cells; first and second current mirror circuits (13,14) which amplify and detect said true and said complementary input signal from said memory cells, respectively; a true and a complementary input signal stabilizing circuit having input nodes connected to said true and complementary input terminals, respectively, and having output nodes connected to input nodes of said first and second current mirror circuits, respectively, for suppressing potential variations in said true and complementary input signals; true and complementary input signal potential holding means (16,17) which are connected with said true and said complementary input terminal, respectively, for holding potentials of the true and complementary input signals and having a current driving capability which is lower than the current driving capability of said memory cell in said memory cell array; and true and complementary sense signal producing circuit (IN3,IN4) for producing a true and a complementary sense signals which determine an operation or non-operation of said true and said complementary input signal potential holding means based on an output logical value of the sense amplifier.
Claim 2
Dependent Claim
219 words
A sense amplifier for a non-volatile semiconductor storage device having a plurality of memory cells in a memory cell array, said sense amplifier comprising: a true and a complementary input terminal (TI, TII) for receiving a true and a complementary input signal (SI, SII) from said memory cells; first and second current mirror circuits (13,14) which amplify and detect said true and said complementary input signal from said memory cells, respectively; a true and a complementary input signal stabilizing circuit having input nodes connected to said true and complementary input terminals, respectively, and having output nodes connected to input nodes of said first and second current mirror circuits, respectively, for suppressing potential variations in said true and complementary input signals; true and complementary input signal potential holding means (16,17) which are connected with said true and said complementary input terminal, respectively, for holding potentials of the true and complementary input signals and having a current driving capability which is lower than the current driving capability of said memory cell in said memory cell array; and true and complementary sense signal producing circuit (IN3,IN4) for producing a true and a complementary sense signals which determine an operation or non-operation of said true and said complementary input signal potential holding means based on an output logical value of the sense amplifier.
Claim 3
Dependent Claim
64 words
A sense amplifier according to claim 1, wherein each of said true and said complementary signal input potential holding means comprises a plurality of active elements which are connected in a cascade form, and a driving element which drives said plurality of active elements in response to each of said true and complementary sense signals from said true and complementary sense signal producing circuit.
Claim 4
Dependent Claim
18 words
A sense amplifier according to claim 2, wherein said active elements are Floating Avalanche MOS transistors (FAMOS transistors).
Claim 5
Dependent Claim
25 words
A sense amplifier according to claim 1, wherein each of said true and said complementary signal input potential holding means is composed of passive elements.
Claim 6
Dependent Claim
79 words
A sense amplifier according to claim 1, wherein said true and complementary sense signal producing circuit comprises first stage and second stage inverter circuits which are connected in cascade, said first stage inverter circuit having an input node connected to an output node of said sense amplifier and an output node connected to said true input signal potential holding means, and said second stage inverter circuit having an output node connected to said complementary input signal potential holding means.