Stable voltage reference circuit with high Vt devices

Claim 2

A voltage reference circuit for generating a stable output voltage at an output node, comprising: a first FET having a first controlled electrode coupled to a supply voltage, a second controlled electrode coupled to the output node, and a gate electrode coupled to one of said first and second controlled electrodes, said first FET having a first threshold voltage; bias means for producing a bias voltage at a bias node, said bias means comprising a current source, and second and third transistors coupled in series between said supply voltage and said current source, said bias node being coupled to the junction between said second and third transistors, said second and third transistors having gate electrodes that are interconnected and coupled to said current source; and first means coupled to said bias node for supplying an overdrive voltage to one of said controlled electrodes of said first FET, said first means having a second threshold voltage that is less than said first threshold voltage, said overdrive voltage being equivalent to a difference between said bias voltage and said second threshold voltage, said first FET and said first means driving the output node to a voltage that is offset from said supply voltage by a voltage equivalent to said first threshold voltage plus said overdrive voltage.

Claim 3

The voltage reference circuit of claim 1, wherein said second threshold voltage is approximately one volt less than said first threshold voltage.

Claim 4

The voltage reference circuit of claim 2, wherein said bias voltage is approximately one volt below said supply voltage.

Claim 5

The voltage reference circuit of claim 3, wherein said first threshold voltage is approximately 1.6 volts.

Claim 6

The voltage reference circuit of claim 4, wherein said supply voltage is approximately 3.3 volts, and said output voltage at said output node is approximately 1.3 volts.

Claim 7

The voltage reference circuit of claim 4, wherein said supply voltage is approximately 4 volts, and said output voltage at said output node is approximately 2 volts.

Claim 8

The voltage reference circuit of claim 4, wherein said supply voltage is at ground potential, and said output voltage at said output node is approximately 2 volts.

Claim 9

A voltage reference circuit for producing a stable voltage at an output node, comprising: bias means for producing a bias voltage at a bias node, said bias means comprising a current source, said first and second transistors coupled in series between a first power supply potential and said current source, said bias node being coupled to the junction between said first and second transistors, said first and second transistors having gate electrodes that are interconnected and coupled to said current source, said bias voltage being offset from said first power supply potential by a first constant voltage; a first FET having a first threshold voltage and a first transconductance, said first threshold voltage being less than said first constant voltage, a first controlled electrode coupled to said first power supply potential, a gate electrode coupled to said bias node, such that said first FET has an overdrive voltage equivalent to a difference between said bias voltage and said first threshold voltage, and a second controlled electrode coupled to the output node; and a second FET having a second threshold voltage that exceeds said first threshold voltage in absolute value and a second transconductance that is substantially equivalent to said first transconductance, a first controlled electrode coupled to the output node, a second controlled electrode coupled to a second power supply potential, and a gate electrode coupled to one of said controlled electrodes of said second FET, said first and second FETs driving the output node to a voltage that is offset from said second power supply potential by an amount equivalent to said second threshold voltage plus said overdrive voltage.

Claim 10

A voltage reference circuit for producing a stable voltage at an output node, comprising: bias means for producing a bias voltage at a bias node, said bias means comprising a current source, said first and second transistors coupled in series between a first power supply potential and said current source, said bias node being coupled to the junction between said first and second transistors, said first and second transistors having gate electrodes that are interconnected and coupled to said current source, said bias voltage being offset from said first power supply potential by a first constant voltage; a first FET having a first threshold voltage and a first transconductance, said first threshold voltage being less than said first constant voltage, a first controlled electrode coupled to said first power supply potential, a gate electrode coupled to said bias node, such that said first FET has an overdrive voltage equivalent to a difference between said bias voltage and said first threshold voltage, and a second controlled electrode coupled to the output node; and a second FET having a second threshold voltage that exceeds said first threshold voltage in absolute value and a second transconductance that is substantially equivalent to said first transconductance, a first controlled electrode coupled to the output node, a second controlled electrode coupled to a second power supply potential, and a gate electrode coupled to one of said controlled electrodes of said second FET, said first and second FETs driving the output node to a voltage that is offset from said second power supply potential by an amount equivalent to said second threshold voltage plus said overdrive voltage.

Claim 11

The voltage reference circuit of claim 8, wherein said second transistor has said second threshold voltage, and said third transistor has said first threshold voltage.

Claim 12

The voltage reference circuit of claim 1, wherein said first FET is selected from a plurality of selectable transistors, each having a transconductance that is different from the transconductances of other ones of said plurality of selectable transistors.

Claim 13

The voltage reference circuit of claim 10, wherein said first FET is selected by coupling a controlled electrode of a selected one of said selectable transistors to the output node.

Claim 14

The voltage reference circuit of claim 11, wherein said first FET is selected by coupling a gate electrode and first and second controlled electrodes of said a selected one of said selectable transistors to one of said first and second controlled electrodes of said selected one of said selectable transistors, said supply voltage, and the output node respectively.

Claim 15

A voltage reference circuit receiving a high power supply potential Vdd and a low power supply potential for producing an output voltage at an output node, comprising: bias means including a bias node for producing a constant voltage of Vdd-1 at said bias node; a first FET having a gate electrode coupled to said bias node, a first controlled electrode coupled to Vdd, and a second controlled electrode, said first FET having a first threshold voltage, said first FET producing a current at said second controlled electrode at a voltage equivalent to the difference between Vdd-1 and said first threshold voltage; a second FET having a first controlled electrode coupled to Vdd and both a gate electrode and a second controlled electrode coupled to the output node, said first FET having a second threshold voltage that is greater than said first threshold voltage; and current mirror means comprising third and fourth FETs having interconnected gate electrodes, said third FET being coupled between said low power supply potential and said second controlled electrode of said first FET, and said fourth FET being coupled between said low power supply potential and the output node, for producing a current into said second FET that is substantially similar to said current produced by said first FET, said third nd fourth FETs having substantially similar transconductances.

Claim 16

A voltage reference circuit receiving a high power supply potential Vdd and a low power supply potential for producing an output voltage at an output node, comprising: bias means including a bias node for producing a constant voltage of Vdd-1 at said bias node; a first FET having a gate electrode coupled to said bias node, a first controlled electrode coupled to Vdd, and a second controlled electrode, said first FET having a first threshold voltage, said first FET producing a current at said second controlled electrode at a voltage equivalent to the difference between Vdd-1 and said first threshold voltage; a second FET having a first controlled electrode coupled to Vdd and both a gate electrode and a second controlled electrode coupled to the output node, said first FET having a second threshold voltage that is greater than said first threshold voltage; and current mirror means comprising third and fourth FETs having interconnected gate electrodes, said third FET being coupled between said low power supply potential and said second controlled electrode of said first FET, and said fourth FET being coupled between said low power supply potential and the output node, for producing a current into said second FET that is substantially similar to said current produced by said first FET, said third nd fourth FETs having substantially similar transconductances.

Claim 17

The voltage reference circuit of claim 13, wherein said bias means comprises, a current source, first and second bias transistors coupled in series between Vdd and said current source, said first and second bias transistors having gate electrodes that are interconnected and coupled to said current source, and a bias node coupled to the junction between said first and second bias transistors and to said gate electrode of said first FET.

Claim 18

The voltage reference circuit of claim 14, wherein said first bias transistor has said second threshold voltage, and said second bias transistor has said first threshold voltage.

Claim 19

The voltage reference circuit of claim 13, wherein said second FET is selected from a plurality of selectable transistors, each having a transconductance that is different from the transconductances of other ones of said plurality of selectable transistors.