Circuit and method for forming a non-volatile memory cell

Claim 2

An electrically erasable, electrically programmable read-only memory cell formed at a face of a semiconductor layer having a first conductivity-type, comprising: a tunnel diode doped region of a second conductivity-type opposite said first conductivity-type formed at said face; a first highly doped region of said second conductivity-type formed in said face; a second highly doped region of said second conductivity-type formed in said face, a sense transistor channel region of said first conductivity-type spacing said first highly doped region from said second highly doped region, at least one of said first and second highly doped regions being spaced from said tunnel diode region; a thin tunnel insulator formed on said face over said tunnel diode doped region, a gate insulator formed on said face over sense transistor channel region; a conductive floating gate having portions formed on said tunnel insulator layer and said gate insulator layer and having lateral margins wherein said floating gate is fork-shaped and includes at least first and second spaced apart fingers connected by a main body, said first finger formed on said tunnel insulator layer and said second finger formed on said gate insulator layer and wherein said main body is substantially larger in surface area than said first and second fingers; and a conductive control gate insulatively disposed over said floating gate so as to be capacitively coupled thereto, lateral margins of said control gate overlapping corresponding lateral margins of said floating gate at all points.

Claim 3

The memory cell of claim 1, wherein said control gate comprises a layer of conductive polysilicon having at least two lateral margins which are largely identical to said lateral margins of said floating gate.

Claim 4

A non-stack memory cell formed at a face of a layer of semiconductor of a first conductivity-type comprising: a tunnel diode region formed in said face, said tunnel diode region of a second conductivity-type opposite said first conductivity-type; a thin insulator tunneling window formed adjacent a portion of said tunnel diode region; a floating gate conductor having a portion formed insulatively adjacent said tunneling window and having a peripheral margin, wherein said floating gate is fork-shaped and includes first and second spaced apart fingers connected by a main body, said main body substantially larger in surface area than said first and second fingers for providing increased capacitive coupling area with said control gate; a control gate conductor insulatively adjacent said floating gate conductor such that a predetermined programming voltage applied to said control gate conductor is capacitively coupled to said floating gate conductor, said control gate conductor having a peripheral margin insulatively overlapping said peripheral margin of said floating gate conductor; circuitry electrically coupled to said control gate conductor for applying said programming voltage to said control gate conductor such that said floating gate conductor is charged with electrons tunneling through said tunneling window; and circuitry electrically coupled to said floating gate for reading said memory cell by detecting a charge induced on said floating gate conductor by said electrons.

Claim 5

A non-stack memory cell formed at a face of a layer of semiconductor of a first conductivity-type comprising: a tunnel diode region formed in said face, said tunnel diode region of a second conductivity-type opposite said first conductivity-type; a thin insulator tunneling window formed adjacent a portion of said tunnel diode region; a floating gate conductor having a portion formed insulatively adjacent said tunneling window and having a peripheral margin, wherein said floating gate is fork-shaped and includes first and second spaced apart fingers connected by a main body, said main body substantially larger in surface area than said first and second fingers for providing increased capacitive coupling area with said control gate; a control gate conductor insulatively adjacent said floating gate conductor such that a predetermined programming voltage applied to said control gate conductor is capacitively coupled to said floating gate conductor, said control gate conductor having a peripheral margin insulatively overlapping said peripheral margin of said floating gate conductor; circuitry electrically coupled to said control gate conductor for applying said programming voltage to said control gate conductor such that said floating gate conductor is charged with electrons tunneling through said tunneling window; and circuitry electrically coupled to said floating gate for reading said memory cell by detecting a charge induced on said floating gate conductor by said electrons.

Claim 6

The non-stack memory cell of claim 3, wherein said circuitry for reading comprises: a sense field effect transistor having first and second source/drain regions of said second conductivity type formed in said face and spaced by a channel area, a second portion of said floating gate disposed insulatively adjacent a portion of said channel area so as to control the conductivity thereof.

Claim 7

The non-stack memory cell of claim 4, wherein said first source/drain of said sense field effect transistor is selectively coupled to a voltage supply and said second source/drain of said sense transistor is coupled to ground.

Claim 8

The non-stack memory cell of claim 5, wherein said first source/drain of said sense transistor is selectively coupled to said voltage supply by a select field effect transistor comprising said second source/drain region and a third source/drain region formed in said face and spaced by a second channel, said sense transistor further comprising a gate conductor insulatively adjacent said second channel to control the conductivity thereof.

Claim 9

The non-stack memory cell of claim 6, wherein said first source/drain region of said sense transistor further comprises said third source/drain region of said select transistor.

Claim 10

The memory cell of claim 7, wherein a first portion of said peripheral margin of said control gate insulatively overlies a second portion of said channel area of said sense transistor controlling the conductivity thereof and a second portion of said peripheral margin of said control gate conductor insulatively overlies a third portion of said channel area of said sense transistor for controlling the conductivity thereof.

Claim 11

A non-volatile memory cell formed at the face of a layer of semiconductor of a first conductivity-type comprising: a first doped source/drain region formed in said layer of semiconductor, said first doped source/drain region of a second conductivity-type opposite said first conductivity-type; a second doped source/drain region of said second conductivity type formed in said layer of semiconductor and spaced from said first source/drain region by a first channel area; a gate conductor insulatively overlying said first channel area for controlling the conductivity thereof; a third doped source/drain region of said second conductivity type formed in said layer of semiconductor and spaced from said second source/drain region by a second channel area, said second channel area being spaced from said first channel area; a tunneling diode doped region of said second conductivity type formed in said layer of semiconductor adjacent said second source/drain region; a thin insulator tunneling window disposed adjacent a portion of said tunneling diode region; a fork-shaped floating gate conductor having a first portion disposed adjacent said thin insulator tunneling window and a second portion disposed insulatively adjacent a portion of said second channel area wherein said floating gate conductor includes first and second spaced apart prongs connected by a main body and wherein and wherein said main body of said floating gate has a surface area substantially larger than a surface area of said first and second prongs; and a control gate conductor with a first portion of disposed insulatively adjacent an upper surface of said floating gate conductor.

Claim 12

A non-volatile memory cell formed at the face of a layer of semiconductor of a first conductivity-type comprising: a first doped source/drain region formed in said layer of semiconductor, said first doped source/drain region of a second conductivity-type opposite said first conductivity-type; a second doped source/drain region of said second conductivity type formed in said layer of semiconductor and spaced from said first source/drain region by a first channel area; a gate conductor insulatively overlying said first channel area for controlling the conductivity thereof; a third doped source/drain region of said second conductivity type formed in said layer of semiconductor and spaced from said second source/drain region by a second channel area, said second channel area being spaced from said first channel area; a tunneling diode doped region of said second conductivity type formed in said layer of semiconductor adjacent said second source/drain region; a thin insulator tunneling window disposed adjacent a portion of said tunneling diode region; a fork-shaped floating gate conductor having a first portion disposed adjacent said thin insulator tunneling window and a second portion disposed insulatively adjacent a portion of said second channel area wherein said floating gate conductor includes first and second spaced apart prongs connected by a main body and wherein and wherein said main body of said floating gate has a surface area substantially larger than a surface area of said first and second prongs; and a control gate conductor with a first portion of disposed insulatively adjacent an upper surface of said floating gate conductor.

Claim 13

The non-volatile memory cell of claim 9, wherein said first prong comprises said first portion of said floating gate conductor and said second prong comprises said second portion of said floating gate conductor.

Claim 14

The non-volatile memory cell of claim 10, wherein said first prong is substantially in parallel to said second prong.

Claim 15

The non-volatile memory cell of claim 9, wherein said control gate includes a sidewall and wherein a first portion of said control gate sidewall is disposed adjacent a second portion of said second channel area and a second portion of said control gate sidewall is disposed adjacent a third portion of said second channel area.

Claim 16

An electrically erasable, electrically programmable read-only memory cell formed at a face of a semiconductor layer having a first conductivity-type, comprising: a tunnel diode doped region of a second conductivity-type opposite said first conductivity-type formed at said face; a first highly doped region of said second conductivity-type formed in said face; a second highly doped region of said second conductivity-type formed in said face, a sense transistor channel region of said first conductivity-type spacing said first highly doped region from said second highly doped region, at least one of said first and second highly doped regions being spaced from said tunnel diode region; a thin tunnel insulator formed on said face over said tunnel diode doped region, a gate insulator formed on said face over sense transistor channel region; a conductive floating gate having a first finger portion adjacent said tunnel insulator layer, a second finger portion adjacent said gate oxide layer, and a third capacitive coupling portion spaced from said sense transistor channel and said tunnel diode, said second and third portions having lateral margins, wherein said third capacitive coupling portion has a surface area substantially larger than said first and second finger portions; and a conductive control gate insulatively disposed over at least said second and third portions of said floating gate so as to be capacitively coupled thereto, lateral margins of said control gate overlapping said lateral margins of said second and third portions of said floating gate.

Claim 17

An electrically erasable, electrically programmable read-only memory cell formed at a face of a semiconductor layer having a first conductivity-type, comprising: a tunnel diode doped region of a second conductivity-type opposite said first conductivity-type formed at said face; a first highly doped region of said second conductivity-type formed in said face; a second highly doped region of said second conductivity-type formed in said face, a sense transistor channel region of said first conductivity-type spacing said first highly doped region from said second highly doped region, at least one of said first and second highly doped regions being spaced from said tunnel diode region; a thin tunnel insulator formed on said face over said tunnel diode doped region, a gate insulator formed on said face over sense transistor channel region; a conductive floating gate having a first finger portion adjacent said tunnel insulator layer, a second finger portion adjacent said gate oxide layer, and a third capacitive coupling portion spaced from said sense transistor channel and said tunnel diode, said second and third portions having lateral margins, wherein said third capacitive coupling portion has a surface area substantially larger than said first and second finger portions; and a conductive control gate insulatively disposed over at least said second and third portions of said floating gate so as to be capacitively coupled thereto, lateral margins of said control gate overlapping said lateral margins of said second and third portions of said floating gate.

Claim 18

The memory cell of claim 13, wherein said control gate is further disposed insulatively adjacent said first portion of said floating gate, said first portion having lateral margins, lateral margins of said control gate overlapping said lateral margins of said first portion of said floating gate.

Claim 19

The memory cell of claim 13, wherein said floating gate is fork-shaped having first and second spaced apart fingers and a main body, said first finger portion of said floating gate forming said finger, said second finger portion of said floating gate forming said second finger and said third capacitive coupling portion of said floating gate forming said main body.

Claim 20

The memory cell of claim 15, wherein said first and second spaced apart fingers are disposed substantially in parallel to each other.

Claim 21

An array of non-stack memory cells formed in columns and in rows disposed at an angle to said columns, at a face of a layer of semiconductor of a first conductivity-type comprising: for each pair of said cells forming each said column, a first select transistor source/drain region formed in said face, said first select transistor source/drain region of a second conductivity-type opposite said first conductivity-type; for each pair of said cells forming each said column, a first sense transistor source/drain region of said second conductivity-type formed in said face; for each cell forming each said pair, a second select transistor source/drain region of said second conductivity type formed in said face and spaced from said first select transistor source/drain region by a select transistor channel; for each cell forming each said pair, a second sense transistor source/drain region of said second conductivity type formed in said face and spaced from said first sense transistor source/drain region by a sense transistor channel; for each cell, a tunnel diode region of a second conductivity type formed in said face; for each cell, a thin insulator tunneling window disposed adjacent at least a portion of said tunneling diode region; for each row, a gate conductor insulatively overlying said select transistor channel of each said cell forming said row; for each cell, a fork-shaped floating gate including first and second spaced apart finger portions and a main body with a surface area substantially larger than a surface area of said finger portions wherein said first finger portion is disposed adjacent said thin insulator tunneling window and said second finger portion is disposed insulatively adjacent said sense transistor channel area; and for each row, an elongated control gate conductor insulating overlying at least a portion of each said floating gates of said cells in said row.

Claim 22

An array of non-stack memory cells formed in columns and in rows disposed at an angle to said columns, at a face of a layer of semiconductor of a first conductivity-type comprising: for each pair of said cells forming each said column, a first select transistor source/drain region formed in said face, said first select transistor source/drain region of a second conductivity-type opposite said first conductivity-type; for each pair of said cells forming each said column, a first sense transistor source/drain region of said second conductivity-type formed in said face; for each cell forming each said pair, a second select transistor source/drain region of said second conductivity type formed in said face and spaced from said first select transistor source/drain region by a select transistor channel; for each cell forming each said pair, a second sense transistor source/drain region of said second conductivity type formed in said face and spaced from said first sense transistor source/drain region by a sense transistor channel; for each cell, a tunnel diode region of a second conductivity type formed in said face; for each cell, a thin insulator tunneling window disposed adjacent at least a portion of said tunneling diode region; for each row, a gate conductor insulatively overlying said select transistor channel of each said cell forming said row; for each cell, a fork-shaped floating gate including first and second spaced apart finger portions and a main body with a surface area substantially larger than a surface area of said finger portions wherein said first finger portion is disposed adjacent said thin insulator tunneling window and said second finger portion is disposed insulatively adjacent said sense transistor channel area; and for each row, an elongated control gate conductor insulating overlying at least a portion of each said floating gates of said cells in said row.

Claim 23

The array of claim 17 and further comprising a plurality of first conductive control lines, each said first control lines associated with a column for electrically coupling each said first sense transistor source/drain regions forming said column.

Claim 24

The array of claim 18 and further comprising a plurality of second conductive control lines, each said second control line associated with an associated column for electrically coupling each said first select transistor source/drain regions forming said column.

Claim 25

The array of claim 17, wherein said control gate includes a sidewall and portions of said sidewall are disposed insulatively adjacent respective portions of said sense transistor channels of said cells in said row.

Claim 26

The non-stack memory cell of claim 4 wherein said second portion of said floating gate comprises said second finger.