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US5227322A
Expired / Lapsed
US
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Method for manufacturing a highly integrated semiconductor device having a capacitor of large capacitance
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-04-14
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Granted: 1993-07-13
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Expires: 2012-04-14
Abstract
Abstract Disclosed is a method comprising forming a first electrode by forming a conductive layer on a semiconductor substrate, forming an etching mask on the conductive layer, etching the conductive layer and defining the conductive layer into cell units; and forming a dielectric film and a second electrode or the first electrode. Also disclosed is a method comprising forming a first electrode by forming a conductive structure on a semiconductor substrate, forming an etching mask on the conductive structure and etching the conductive structure; and forming a dielectric film and a second electrode on the first electrode. An insulating layer including pin holes such as a silicon nitride layer is formed on the conductive structure or the conductive layer; which is exposed under an oxidative atmosphere. The surface portion of the conductive structure or conductive layer is oxidized to form silicon oxide islands to be used as an etching mask. Since the method requires no specific process conditions, it is simple and extends the effective area of the cell capacitor, and is also applicable to various capacitor types.
Inventors
- 👤 Jae-hong Ko
- 👤 Hee-seok Kim
- 👤 Sung-tae Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:16
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
84 words
A method for manufacturing a highly integrated semiconductor device having a capacitor of large capacitance comprising the steps of: forming a first electrode by forming a conductive layer on a semiconductor substrate, forming an insulating layer including pin holes on said conductive layer, forming an etching mask via said pin holes by an oxidation process, removing said insulating layer, etching said conductive layer, and defining said conductive layer into cell units; and forming a dielectric film and a second electrode on said first electrode.
Claim 2
Independent Claim
84 words
A method for manufacturing a highly integrated semiconductor device having a capacitor of large capacitance comprising the steps of: forming a first electrode by forming a conductive layer on a semiconductor substrate, forming an insulating layer including pin holes on said conductive layer, forming an etching mask via said pin holes by an oxidation process, removing said insulating layer, etching said conductive layer, and defining said conductive layer into cell units; and forming a dielectric film and a second electrode on said first electrode.
Claim 3
Dependent Claim
24 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 1, wherein said etching mask is constituted by silicon oxide islands.
Claim 4
Dependent Claim
22 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 1, wherein conductive layer is etching by anisotropic etching.
Claim 5
Dependent Claim
23 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 1, wherein said insulating layer is a silicon nitride layer.
Claim 6
Dependent Claim
34 words
A method for manufacturing a semiconductor as claimed in claim 4, wherein said silicon nitride layer is formed by depositing silicon nitride by the LPCVD method to a thickness of about 30 Å-500 Å.
Claim 7
Dependent Claim
45 words
A method for manufacturing a semiconductor as claimed in claim 1, wherein said etching mask is formed by exposing said conductive layer on which a insulating layer including pin holes is formed under an oxidative atmosphere and oxidizing the surface portion of said conductive layer.
Claim 8
Dependent Claim
25 words
A method for manufacturing a semiconductor as claimed in claim 1, further comprising the step of removing said etching mask after etching said conductive layer.
Claim 9
Dependent Claim
19 words
A method for manufacturing a semiconductor as claimed in claim 7, said etching mask is removed by wet etching.
Claim 10
Dependent Claim
47 words
A method for manufacturing a semiconductor as claimed in claim 1, further comprising the step of coating a conductive material on said conductive layer after etching said conductive layer or on said first electrode after defining said conductive layer into cell units to form said first electrode.
Claim 11
Dependent Claim
20 words
A method for manufacturing a semiconductor as claimed in claim 9, wherein said conductive material is an impurity-implanted polycrystalline silicon.
Claim 12
Dependent Claim
29 words
A method for manufacturing a semiconductor as claimed in claim 10, wherein said conductive material is coated by depositing polycrystalline silicon via CVD method and then implantating an impurity.
Claim 13
Dependent Claim
25 words
A method for manufacturing a semiconductor as claimed in claim 9, said conductive material is coated by depositing in a thickness of 50 Å-500 Å.
Claim 14
Dependent Claim
24 words
A method for manufacturing a semiconductor as claimed in claim 1, wherein said conductive layer is composed of polycrystalline silicon implanted with an impurity.
Claim 15
Dependent Claim
35 words
A method for manufacturing a semiconductor as claimed in claim 13, wherein said conductive layer is a polycrystalline silicon layer formed by depositing a polycrystalline silicon on a semiconductor substrate and then implanting an impurity.
Claim 16
Dependent Claim
28 words
A method for manufacturing a semiconductor as claimed in claim 1, said conductive layer is formed on the inner surface of a trench formed in a silicon substrate.
Claim 17
Dependent Claim
35 words
A method for manufacturing a semiconductor as claimed in claim 1, wherein said conductive layer is defined into cell units by forming a photoresist pattern on said conductive layer and anistropically etching said conductive layer.
Claim 18
Dependent Claim
23 words
A method for manufacturing a semiconductor as claimed in claim 1, wherein said capacitor is a stacked capacitor, or a stacked trench capacitor.
Claim 19
Independent Claim
77 words
A method for manufacturing a highly integrated semiconductor device having a capacitor of large capacitance comprising the steps of: forming a first electrode by forming a conductive structure on a semiconductor substrate, forming an insulating layer including pin holes on said conductive structure, forming an etching mask via said pin holes by an oxidation process, removing said insulating layer, and etching said conductive structure; and forming a dielectric film and a second electrode on said first electrode.
Claim 20
Independent Claim
77 words
A method for manufacturing a highly integrated semiconductor device having a capacitor of large capacitance comprising the steps of: forming a first electrode by forming a conductive structure on a semiconductor substrate, forming an insulating layer including pin holes on said conductive structure, forming an etching mask via said pin holes by an oxidation process, removing said insulating layer, and etching said conductive structure; and forming a dielectric film and a second electrode on said first electrode.
Claim 21
Dependent Claim
22 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 18, wherein said etching mask comprises silicon oxide islands.
Claim 22
Dependent Claim
23 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 18, wherein said conductive structure is etched by isotropic etching.
Claim 23
Dependent Claim
23 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 18, wherein said insulating layer is a silicon nitride layer.
Claim 24
Dependent Claim
36 words
A method for manufacturing a highly integrated semiconductor as claimed in claim 21, wherein said silicon nitride layer is formed by depositing silicon nitride by the LPCVD method to a thickness of about 30 Å-500 Å.
Claim 25
Dependent Claim
49 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 18, wherein said etching mask is formed by exposing the conductive structure on which an insulating layer including pin holes is formed under an oxidative atmosphere and then oxidizing the surface portion of the conductive structure.
Claim 26
Dependent Claim
28 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 18, further comprising the step of removing said etching mask after etching said conductive structure.
Claim 27
Dependent Claim
21 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 24, said etching mask is removed by wet-etching.
Claim 28
Dependent Claim
32 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 18, further comprising the step of coating a conductive material on said conductive structure after etching said conductive structure.
Claim 29
Dependent Claim
23 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 26, wherein said conductive material is an impurity-implanted polycrystalline silicon.
Claim 30
Dependent Claim
33 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 27, wherein said conductive material is coated by depositing polycrystalline silicon via a CVD method and then implantating an impurity.
Claim 31
Dependent Claim
28 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 26, said conductive material is coated by depositing in a thickness of 50 Å-500 Å.
Claim 32
Dependent Claim
32 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 18, wherein said conductive structure is composed of polycrystalline silicon or a single crystalline silicon implanted with an impurity.
Claim 33
Dependent Claim
43 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 30, wherein said conductive structure is a polycrystalline silicon pattern formed by depositing polycrystalline silicon on a semiconductor substrate, implanting an impurity and then patterning via an ordinary lithography process.
Claim 34
Dependent Claim
31 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 30, said conductive structure is formed on the inner surface of a trench formed in a silicon substrate.
Claim 35
Dependent Claim
31 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 30, wherein said conductive structure is the inner surface portion of a trench formed in said semiconductor substrate.
Claim 36
Dependent Claim
41 words
A method for manufacturing a highly integrated semiconductor device as claimed in claim 18, wherein said capacitor is a stacked capacitor, a trench capacitor, a stacked-trench capacitor, a cylindrical capacitor, a pin structured capacitor, a hollow capacitor or a Box-structured capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-12 | 1997-01-11 | 1997-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-12 | 2001-01-11 | 2001-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-12 | 2005-01-11 | 2005-07-13 | $7700.00 | Window Closed / Lapsed |