Semiconductor memory device for self-correcting data output errors by taking the logical product of first and second identical data outputs

Claim 2

A self-error-correcting semiconductor memory device comprising: a data bus being charged to a predetermined voltage; a programmable ROM being interconnected to said data bus and including a first address for storing first data and a second address corresponding to the first address for storing second data identical to the first data, said data bus generating third data representative of a logical product of the first data and the second data for error correction; an address designating circuit being electrically connected to said programmable ROM through said data bus for outputting first and second address designating signals specifying the first and second addresses, respectively, said address designating circuit outputting said second address designating signal in response to a control signal from a control circuit by converting the first address designating signal into the second address designating signal; at least one temporary circuit being connected to said data bus for temporarily storing data outputted to said data bus from said programmable ROM; and said control circuit being electrically connected to said address designating circuit for outputting the control signal for obtaining the second address designating signal, a first read signal for causing data stored in said programmable ROM to be outputted to said data bus, a write signal for causing data existing in said data bus to be inputted to said at least one temporary circuit, and a second read signal for causing data stored in said at least one temporary circuit to be outputted to said data bus; whereby the first data stored in said first address is read out to said data bus in response to said first address designating signal and said first read signal, and said first data existing in said data bus is inputted to said at least one temporary circuit in response to said write signal; the second data stored in said second address is read out to said data bus in response to the second address designating signal and the first read signal; and the third data is formed by reading the first data stored in said at least one temporary circuit out to said data bus in response to the second read signal and taking the logical product of the first data and the second data, thereafter storing the third data in said at least one temporary register in response to the write signal.

Claim 3

A self-error-correcting semiconductor memory device in accordance with claim 1, wherein said programmable ROM includes a first address area including the first address and a second address area including the second address; said first address area having an address range from 4000H to 47FFH and said second address area having an address range from 4800H to 4FFFH.

Claim 4

A self-error-correcting semiconductor memory device in accordance with claim 1, wherein said address designating circuit includes a programmable counter for storing data designating said first address and an address changing circuit for changing data designating said first address into another data for designating said second address in response to the control signal.

Claim 5

A self-error-correcting semiconductor memory device in accordance with claim 1, wherein said data bus includes a pair of data lines each corresponding to a plurality of bits constituting data to be stored in said programmable ROM; each of said plurality of data lines being connected to a precharge means and charged with a power source by means of said precharge means.

Claim 6

A self-error-correcting semiconductor memory device in accordance with claim 1, wherein said at least one temporary circuit is a register.

Claim 7

A self-error-correcting method for operating a semiconductor memory device which includes: a data bus being charged to a predetermined voltage; a programmable ROM being interconnected to said data bus and including a first address for storing first data and a second address corresponding to the first address for storing second data identical to the first data, said data bus generating third data representative of a logical product of the first data and the second data for error correction; an address designating circuit being electrically connected to said programmable ROM through said data bus for outputting first and second address designating signals specifying the first and second addresses, respectively, said address designating circuit outputting said second address designating signal in response to a control signal from a control circuit by converting the first address designating signal into the second address designating signal; at least one temporary register being connected to said data bus for temporarily storing data outputted to said data bus from said programmable ROM; and said control circuit being electrically connected to said address designating circuit for outputting the control signal for obtaining the second address designating signal, a first read signal for causing data stored in said programmable ROM to be outputted to said data bus, a write signal for causing data existing in said data bus to be inputted to said at least one temporary register, and a second read signal for causing data stored in said at least one temporary register to be outputted to said data bus; the method comprising the steps of: (a) reading the first data stored in said first address out to said data bus in response to said first address designating signal and said first read signal; (b) storing the first data read out to said data bus in said at least one temporary register in response to the write signal; (c) sending the control signal to the address designating circuit; (d) reading the second data stored in said second address out to said data bus in response to the second address designating signal and the first read signal; (e) forming said third data by reading the first data stored in said at least one temporary register out to said data bus and taking the logical product of the first data and the second data in response to the second read signal; and (f) storing the third data formed in said data bus into said at least one temporary register in response to the write signal.

Claim 8

A self-error-correcting method for operating a semiconductor memory device which includes: a data bus being charged to a predetermined voltage; a programmable ROM being interconnected to said data bus and including a first address for storing first data and a second address corresponding to the first address for storing second data identical to the first data, said data bus generating third data representative of a logical product of the first data and the second data for error correction; an address designating circuit being electrically connected to said programmable ROM through said data bus for outputting first and second address designating signals specifying the first and second addresses, respectively, said address designating circuit outputting said second address designating signal in response to a control signal from a control circuit by converting the first address designating signal into the second address designating signal; at least one temporary register being connected to said data bus for temporarily storing data outputted to said data bus from said programmable ROM; and said control circuit being electrically connected to said address designating circuit for outputting the control signal for obtaining the second address designating signal, a first read signal for causing data stored in said programmable ROM to be outputted to said data bus, a write signal for causing data existing in said data bus to be inputted to said at least one temporary register, and a second read signal for causing data stored in said at least one temporary register to be outputted to said data bus; the method comprising the steps of: (a) reading the first data stored in said first address out to said data bus in response to said first address designating signal and said first read signal; (b) storing the first data read out to said data bus in said at least one temporary register in response to the write signal; (c) sending the control signal to the address designating circuit; (d) reading the second data stored in said second address out to said data bus in response to the second address designating signal and the first read signal; (e) forming said third data by reading the first data stored in said at least one temporary register out to said data bus and taking the logical product of the first data and the second data in response to the second read signal; and (f) storing the third data formed in said data bus into said at least one temporary register in response to the write signal.

Claim 9

A self-error-correcting method in accordance with claim 6, wherein the third data is identical to either of the first data and the second data.