US5247478A
Expired / Lapsed
US
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Programmable transfer-devices
Assignee: Altera Corp
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Filing: 1992-03-06
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Granted: 1993-09-21
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Expires: 2012-03-06
Abstract
Abstract A programmable, non-volatile transfer-device includes floating gate structures to control the transfer of signals from a set of inputs to a single output. Each floating gate structure includes two gates, logically coupled to each other in a master/slave mode, whereby the programming of the first gate controls the operation of the second gate. The floating gate structures are combined to implement a programmable multiplexer, without the use of static-RAM cells.
Inventors
- 👤 Anil Gupta
- 👤 Richard G. Cliff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:01
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
196 words
An EPROM programmable logic device for transferring any desired one of a plurality of inputs to a single output comprising: a plurality of transfer-device elements, each element including a first EPROM transistor having an input, an output, a gate, and a floating gate, and a second EPROM transistor having an input, an output, a gate, and a floating gate, the floating gates of said first and second transistors being connected together; means for connecting each of said inputs of said logic device to the input of the second transistor of a respective one of said elements; means for connecting said output of the second transistor of each of said elements to the output of said programmable logic device; means for using the first transistor of each of said elements to determine an amount of charge stored on the floating gate of said first and second transistors of each of said elements so that the second transistors of all but one of said elements are rendered non-conducting despite the application of enabling signals to the gates of all of said second transistors; and means for applying enabling signals to the gates of all of said second transistors.
Claim 2
Dependent Claim
196 words
An EPROM programmable logic device for transferring any desired one of a plurality of inputs to a single output comprising: a plurality of transfer-device elements, each element including a first EPROM transistor having an input, an output, a gate, and a floating gate, and a second EPROM transistor having an input, an output, a gate, and a floating gate, the floating gates of said first and second transistors being connected together; means for connecting each of said inputs of said logic device to the input of the second transistor of a respective one of said elements; means for connecting said output of the second transistor of each of said elements to the output of said programmable logic device; means for using the first transistor of each of said elements to determine an amount of charge stored on the floating gate of said first and second transistors of each of said elements so that the second transistors of all but one of said elements are rendered non-conducting despite the application of enabling signals to the gates of all of said second transistors; and means for applying enabling signals to the gates of all of said second transistors.
Claim 3
Dependent Claim
57 words
The apparatus defined in claim 1 wherein said means for using the first transistor of each of said elements comprises: a word line connected to said gate of said first transistor; a bit line connected to said input of said first transistor; and means for momentarily applying high voltages to said word line and said bit line.
Claim 4
Independent Claim
37 words
The apparatus defined in claim i wherein said programmable logic device comprises: a memory plane containing each said first transistor of each said element; and a logic plane containing each said second transistor of each said element.
Claim 5
Dependent Claim
16 words
The apparatus defined in claim 1 wherein each of said first transistors is an EEPROM transistor.
Claim 6
Dependent Claim
16 words
The apparatus defined in claim 1 wherein each of said first transistors is a FLASH transistor.
Claim 7
Dependent Claim
263 words
An EPROM programmable logic device for transferring any desired one of a plurality of inputs to a single output comprising: a plurality of transfer-device elements, each element including first, second, third, and fourth EPROM transistors each having an input, an output, a gate, and a floating gate, the floating gates of said first and second EPROM transistors being connected together, and the floating gates of said third and fourth EPROM transistors being connected together, each of said elements also including an N-channel transistor having an input, an output, and a gate, the outputs of said second and fourth EPROM transistors being connected to the gate of said N-channel transistor; means for connecting each of said inputs of said programmable logic device to the input of the N-channel transistor of a respective one of said elements; means for connecting said output of the N-channel transistor of each of said elements to the output of said programmable logic device; means for applying a logic 1 signal to the inputs of all of said second EPROM transistors; means for applying a logic 0 signal to the inputs of all of said fourth EPROM transistors; and means for using the first and third EPROM transistors of each of said elements to determine an amount of charge stored on the floating gates of said second and fourth EPROM transistors of each of said elements so that the fourth EPROM transistors of all but one of said elements are rendered conducting and so that the second EPROM transistor of all but said one of said elements is rendered non-conducting.
Claim 8
Dependent Claim
263 words
An EPROM programmable logic device for transferring any desired one of a plurality of inputs to a single output comprising: a plurality of transfer-device elements, each element including first, second, third, and fourth EPROM transistors each having an input, an output, a gate, and a floating gate, the floating gates of said first and second EPROM transistors being connected together, and the floating gates of said third and fourth EPROM transistors being connected together, each of said elements also including an N-channel transistor having an input, an output, and a gate, the outputs of said second and fourth EPROM transistors being connected to the gate of said N-channel transistor; means for connecting each of said inputs of said programmable logic device to the input of the N-channel transistor of a respective one of said elements; means for connecting said output of the N-channel transistor of each of said elements to the output of said programmable logic device; means for applying a logic 1 signal to the inputs of all of said second EPROM transistors; means for applying a logic 0 signal to the inputs of all of said fourth EPROM transistors; and means for using the first and third EPROM transistors of each of said elements to determine an amount of charge stored on the floating gates of said second and fourth EPROM transistors of each of said elements so that the fourth EPROM transistors of all but one of said elements are rendered conducting and so that the second EPROM transistor of all but said one of said elements is rendered non-conducting.
Claim 9
Dependent Claim
81 words
The apparatus defined in claim 6 wherein said means for using the first and third EPROM transistors in each of said elements comprises: a word line connected to said gate of said first EPROM transistor and said third EPROM transistor; a first bit line connected to said input of said first EPROM transistor; a second bit line connected to said input of said third EPROM transistor; and means for momentarily applying high voltages to said word line and said bit line.
Claim 10
Dependent Claim
47 words
The apparatus defined in claim 6 wherein said programmable logic device comprises: a memory plane containing said first EPROM transistor and said third EPROM transistor of each said element; and a logic plane containing said second EPROM transistor and said fourth EPROM transistor of each said element.
Claim 11
Dependent Claim
19 words
The apparatus defined in claim 6 wherein each of said first and third EPROM transistors is an EEPROM transistor.
Claim 12
Dependent Claim
19 words
The apparatus defined in claim 6 wherein each of said first and third EPROM transistors is a FLASH transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-20 | 1997-03-22 | 1997-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-20 | 2001-03-22 | 2001-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-20 | 2005-03-22 | 2005-09-21 | $7700.00 | Window Closed / Lapsed |