Adaptive segment control and method for simulating a multi-segment cache

Claim 2

A computer-implemented method of controlling performance of a first cache memory in a storage system, the method comprising the computer-implemented steps of: segmenting the first cache memory to operate at a selected working segmentation level; monitoring instructions transmitted by a host computer and received by the first cache memory; segmenting a plurality of test cache tables, such that one table operates at the selected working segmentation level and the other test cache tables simultaneously operate at different segmentation levels; monitoring instructions transmitted by the host computer and received by the plurality of test cache tables; determining a hit ratio for each test cache table based upon the monitored instructions; comparing the hit ratios of the test cache tables; determining which test cache table obtains a highest hit ratio; and adjusting the selected working segmentation level to equal the segmentation level of the test cache table having the highest hit ratio.

Claim 3

The method of claim 1 wherein the step of monitoring instructions received by the plurality of test cache tables comprises the step of storing the instructions in an instruction queue.

Claim 4

The method of claim 2 wherein the step of storing the instructions comprises the step of storing the consecutively received instructions.

Claim 5

The method of claim 2 and further comprising the steps of: flushing the instruction queue after the number of stored instructions is equal to a queue limit; and repeating the step of storing the instructions after performing the step of flushing the instruction queue.

Claim 6

The method of claim 4 and further comprising the step of waiting to repeat the step of storing the instructions until after the number of instructions received subsequently from the host computer is equal to a wait count.

Claim 7

The method of claim 2 wherein the step of storing the instructions comprises the steps of: storing a starting address for each instruction; storing a block length which is indicative of the number of consecutive blocks, beginning at the starting address, that are required by each instruction; and storing an instruction type for each instruction.

Claim 8

The method of claim 1 wherein the step of segmenting a plurality of test cache tables comprises the steps of: segmenting a first test cache table to operate at the selected working segmentation level; and segmenting a second test cache table to operate at a selected test segmentation level, the test segmentation level being different from the working segmentation level.

Claim 9

The method of claim 7 wherein the step of segmenting the second test cache table comprises the step of selecting the test segmentation level from entries within a look-up table, wherein the table includes all selectable segmentation levels.

Claim 10

The method of claim 8 wherein the step of selecting the test segmentation level comprises the step of indexing between entries within the look-up table.

Claim 11

The method of claim 8 wherein the selectable segmentation levels range from 1 to 16.

Claim 12

The method of claim 7 wherein the step of monitoring instructions received by the plurality of test cache tables comprises the step of storing the instructions in an instruction queue and wherein the step of determining which test cache table obtains the highest hit ratio comprises the steps of: performing hit ratio simulations on the first and second test cache tables by executing a selected number of instructions stored in the instruction queue; maintaining first and second hit ratio values for the first and second test cache tables, respectively; and comparing the first and second hit ratio values after execution of the selected number of stored instructions.

Claim 13

The method of claim 11 wherein the step of adjusting the working segmentation level comprises the step of adjusting the working segmentation level to equal the test segmentation level when the second hit ratio value is greater than the first hit ratio value.

Claim 14

The method of claim 11 and further comprising the step of repeating the steps of storing instructions, segmenting the first and second test cache tables, performing hit ratio simulations, maintaining first and second hit ratio values, comparing the first and second hit ratio values and adjusting the working segmentation level.

Claim 15

The method of claim 11 and further comprising the steps of: performing a memory operation on the storage system in response to each instruction received from the host computer; operating the storage system in a busy state while performing each memory operation; and returning the storage system to an idle state after completion of each memory operation.

Claim 16

The method of claim 14 wherein the steps of performing hit ratio simulations is performed when the storage system is in the idle state and comprises the steps of: executing one of the stored instructions on the first and second test cache tables when the instruction queue contains at least one stored instruction and the storage system is in the idle state; repeating the step of executing one of the stored instructions until the selected number of stored instructions have been executed; and returning the storage system to the idle state when the instruction queue is empty.

Claim 17

The method of claim 14 and further comprising the steps of: suspending performance of the step of executing one of the stored instructions upon receipt of an instruction from the host computer; performing the step of performing a memory operation in response to the received instruction; and resuming performance of the step of executing one of the stored instructions upon completion of the memory operation.

Claim 18

A computer-implemented method of automatically controlling performance of a first cache memory in a disc drive controller, the method comprising the computer-implemented steps of: segmenting the cache to operate at a selected working segmentation level; receiving instructions transmitted by a host computer; performing memory operations with the disc drive controller in response to the received instructions; storing the received instructions in an instruction queue; segmenting a first test cache table to operate at the selected working segmentation level; segmenting a second test cache table to operate at a selected test segmentation level, the test segmentation level being different from the working segmentation level; performing hit ratio simulations on the first and second test cache tables by executing a selected number of stored instructions; maintaining first and second hit ratio values for the first and second test cache tables, respectively; comparing the first and second hit ratio values after execution of the selected number of stored instructions; adjusting the working segmentation level to equal the test segmentation level when the second hit ratio value is greater than the first hit ratio value; and repeating the steps of storing the received instructions, segmenting the first and second test tables, performing hit ratio simulations, maintaining first and second hit ratio values, an comparing the first and second hit ratio values, after completion of the step of adjusting the working segmentation level.

Claim 19

A computer-implemented method of automatically controlling performance of a first cache memory in a disc drive controller, the method comprising the computer-implemented steps of: segmenting the cache to operate at a selected working segmentation level; receiving instructions transmitted by a host computer; performing memory operations with the disc drive controller in response to the received instructions; storing the received instructions in an instruction queue; segmenting a first test cache table to operate at the selected working segmentation level; segmenting a second test cache table to operate at a selected test segmentation level, the test segmentation level being different from the working segmentation level; performing hit ratio simulations on the first and second test cache tables by executing a selected number of stored instructions; maintaining first and second hit ratio values for the first and second test cache tables, respectively; comparing the first and second hit ratio values after execution of the selected number of stored instructions; adjusting the working segmentation level to equal the test segmentation level when the second hit ratio value is greater than the first hit ratio value; and repeating the steps of storing the received instructions, segmenting the first and second test tables, performing hit ratio simulations, maintaining first and second hit ratio values, an comparing the first and second hit ratio values, after completion of the step of adjusting the working segmentation level.

Claim 20

The method of claim 17 wherein the step of storing the received instructions comprises the step of storing consecutively received instructions.

Claim 21

The method of claim 17 and further comprising the steps of: flushing the instruction queue after the number of stored instructions is equal to a queue limit; and repeating the step of storing the received instructions after performing the step of flushing the instruction queue.

Claim 22

The method of claim 19 and further comprising the step of waiting to repeat the step of storing the received instructions until after the number of instructions received from the host computer is equal to a wait count.

Claim 23

The method of claim 17 wherein the step of receiving instructions comprises the steps of: receiving a starting address for each instruction; receiving a block length requested by each instruction; and receiving an instruction type for each instruction.

Claim 24

The method of claim 17 wherein the step of segmenting the second test cache table comprises the step of selecting the test segmentation level from entries within a look-up table, wherein the entries comprise all selectable segmentation levels.

Claim 25

The method of claim 22 wherein the step of selecting the test segmentation level comprises the step of indexing between entries within the look-up table.

Claim 26

The method of claim 22 wherein the selectable segmentation levels range from 1 to 16.

Claim 27

The method of claim 17 wherein the step of performing memory operations in response to the received instructions comprises the steps of: removing the disk drive controller from an idle state; operating the disk drive controller in a busy state while performing each memory operation; and returning the disk drive controller to the idle state after completion of each memory operation.

Claim 28

The method of claim 25 wherein the step of performing hit ratio simulations comprises the steps of: executing one of the stored instructions on the first and second virtual cache tables when the instruction queue contains at least one stored instruction and the disk drive controller is in the idle state; and repeating the step of executing one of the stored instructions until the selected number of stored instructions have been executed.

Claim 29

The method of claim 26 wherein the step of performing hit ratio simulations further comprises the step of returning the storage system to the idle state when the instruction queue is empty.

Claim 30

The method of claim 26 and further comprising the steps of: suspending performance of the step of executing one of the stored instructions after receipt of an instruction from the host computer; performing the step of performing a memory operation in response to the received instruction; and resuming performance of the step of executing one of the stored instructions after completion of the memory operation.

Claim 31

A computer-implemented adaptive segment control assembly for a storage system, the assembly comprising: a multi-segment cache memory having a selectable working segmentation level; means, connected to the multi-segment cache memory, for selecting the working segmentation level; means, connected to the multi-segment cache memory, for receiving instructions transmitted by a host computer and applying the received instructions to the multi-segment cache memory; a plurality of test cache tables which are separate from the multi-segment cache memory; an instruction queue which is connected to the plurality of test cache tables and is connected to receive instructions transmitted by the host computer and store the received instructions; means, connected to the plurality of test cache tables, for segmenting the plurality of test cache tables such that one table operates at the selected working segmentation level and the other tables simultaneously operate at different segmentation levels; means, connected to the test cache tables and the instruction queue, for performing hit ratio simulations on the test cache tables by executing a selected number of stored instructions, maintaining a hit ratio for each test cache table, and determining which test cache table obtains the highest hit ratio; and means, connected to the means for selecting the working segmentation level and to the means for performing hit ratio simulations, for adjusting the selected working segmentation level to equal the segmentation level of the test cache table having the highest hit ratio.

Claim 32

A computer-implemented adaptive segment control assembly for a storage system, the assembly comprising: a multi-segment cache memory having a selectable working segmentation level; means, connected to the multi-segment cache memory, for selecting the working segmentation level; means, connected to the multi-segment cache memory, for receiving instructions transmitted by a host computer and applying the received instructions to the multi-segment cache memory; a plurality of test cache tables which are separate from the multi-segment cache memory; an instruction queue which is connected to the plurality of test cache tables and is connected to receive instructions transmitted by the host computer and store the received instructions; means, connected to the plurality of test cache tables, for segmenting the plurality of test cache tables such that one table operates at the selected working segmentation level and the other tables simultaneously operate at different segmentation levels; means, connected to the test cache tables and the instruction queue, for performing hit ratio simulations on the test cache tables by executing a selected number of stored instructions, maintaining a hit ratio for each test cache table, and determining which test cache table obtains the highest hit ratio; and means, connected to the means for selecting the working segmentation level and to the means for performing hit ratio simulations, for adjusting the selected working segmentation level to equal the segmentation level of the test cache table having the highest hit ratio.

Claim 33

The adaptive segment control assembly of claim 29 and further comprising: means for causing the instruction queue to be flushed after the number of stored instructions is equal to a queue limit; and wherein the instruction queue continues to store instructions after the instruction queue has been flushed.

Claim 34

The adaptive segment control assembly of claim 30 and further comprising means for delaying storage of the instructions until after the number of instructions received subsequently from the host computer is equal to a wait count.

Claim 35

The adaptive segment control assembly of claim 29 where in the plurality of test cache tables comprises first and second test cache tables and wherein the computer-implemented adaptive segment control assembly further comprises: means for segmenting the first test cache table at the selected working segmentation level; and means for segmenting a second test cache table at a selected test segmentation level, the test segmentation level being different from the working segmentation level.

Claim 36

The adaptive segment control assembly of claim 32 wherein the means for segmenting the second test cache table comprises a look-up table having entries comprising all selectable segmentation levels.

Claim 37

The adaptive segment control assembly of claim 33 wherein the means for segmenting the second test cache table further comprises means for indexing between entries within the look-up table.

Claim 38

The adaptive segment control assembly of claim 33 wherein the selectable segmentation levels range from 1 to 16.

Claim 39

The adaptive segment control assembly of claim 32 wherein the means for adjusting the working segmentation level comprises means for adjusting the working segmentation level to equal the test segmentation level when the hit ratio of the second test cache table is greater than the hit ratio of the first test cache table.

Claim 40

The adaptive segment control assembly of claim 32 and further comprising: means for performing a memory operation of the storage system in response to each instruction received from the host computer; means for operating the storage system in a busy state while performing each memory operation; and means for returning the storage system to an idle state after completion of each memory operation.

Claim 41

The adaptive segment control assembly of claim 37 wherein the means for performing hit ratio simulations comprises: means for executing one of the selected number of stored instructions on the first and second test cache tables when the instruction queue contains at least one stored instruction and the storage system is in the idle state; and means for returning the storage system to the idle state when the instruction queue is empty.

Claim 42

The adaptive segment control assembly of claim and further comprising: means for suspending execution of a stored instruction upon receipt of an instruction from the host computer; means for performing a memory operation in response to the received instructions; and means for causing execution of the stored instruction to resume upon completion of the memory operation.