US5258955A — Pre-charging method for the reading of memories

Claim 1

Independent Claim 199 words

A pre-charging and reading circuit for an integrated circuit memory comprising: a bit line for communicating with a memory cell, said memory cell having either a programmed state or an unprogrammed state; a pre-charging node; a first transistor for selectively connecting said bit line to said pre-charging node during a reading operation; a current/voltage converter connected to said pre-charging node and having an output for communicating a signal to a differential amplifier, said signal representing said state of said memory cell; a pre-charging transistor coupling said pre-charging node to a first voltage source; a servo-control circuit connected between said pre-charging node and a second voltage source, said servo-control circuit having an output connected to the gate of said pre-charging transistor, said servo-control circuit producing a first output voltage on said output during a pre-charging phase and a second output voltage on said output during a reading phase, said first output voltage driving said pre-charging transistor so as to cause said pre-charging node to charge toward a first voltage value, said second output voltage driving said pre-charging transistor so as to maintain said pre-charging node at a desired voltage value, wherein said first voltage value exceeds said desired voltage value.

Claim 2

Dependent Claim 199 words

A pre-charging and reading circuit for an integrated circuit memory comprising: a bit line for communicating with a memory cell, said memory cell having either a programmed state or an unprogrammed state; a pre-charging node; a first transistor for selectively connecting said bit line to said pre-charging node during a reading operation; a current/voltage converter connected to said pre-charging node and having an output for communicating a signal to a differential amplifier, said signal representing said state of said memory cell; a pre-charging transistor coupling said pre-charging node to a first voltage source; a servo-control circuit connected between said pre-charging node and a second voltage source, said servo-control circuit having an output connected to the gate of said pre-charging transistor, said servo-control circuit producing a first output voltage on said output during a pre-charging phase and a second output voltage on said output during a reading phase, said first output voltage driving said pre-charging transistor so as to cause said pre-charging node to charge toward a first voltage value, said second output voltage driving said pre-charging transistor so as to maintain said pre-charging node at a desired voltage value, wherein said first voltage value exceeds said desired voltage value.

Claim 3

Dependent Claim 49 words

A pre-charging and reading circuit in accordance with claim 1 further comprising a selection circuit adapted to change said output of said servo-control circuit from said first output voltage to said second output voltage when the voltage on the bit line is substantially equal to the desired voltage value.

Claim 4

Dependent Claim 71 words

A pre-charging and reading circuit in accordance with claim 1, wherein the servo-control circuit has second, third, and fourth transistors, each having a respective gate, the type of conductivity of said second transistor being opposite to the type of conductivity of said third and fourth transistors, the channel width to channel length ratio of said third transistor being different from the channel width to channel length ratio of said fourth transistor.

Claim 5

Dependent Claim 28 words

A pre-charging and reading circuit in accordance with claim 3 wherein said gate of each of said second, third and fourth transistor is coupled to said pre-charging node.

Claim 6

Dependent Claim 29 words

A pre-charging and reading circuit in accordance with claim 4 wherein said second transistor is a P type transistor and said third and fourth transistors are N type transistors.

Claim 7

Dependent Claim 75 words

A pre-charging and reading circuit in accordance with claim 2 wherein said selection circuit comprises a first selection transistor connected in series with a third transistor and a second selection transistor connected in series with a fourth transistor, said first selection transistor being selected by an activating pulse to the gate of said first selection transistor, and said second selection transistor being selected by an activating pulse to the gate of said second selection transistor.

Claim 8

Dependent Claim 60 words

A pre-charging and reading circuit in accordance with claim 6 wherein said activating pulse to the gate of said selection transistors comprises a first clock signal to the gate of said first selection transistor and a second clock signal to the gate of said second selection transistor said second clock signal being the logic complement to said first clock signal.

Claim 9

Dependent Claim 100 words

A pre-charging and reading circuit in accordance with claim 1 wherein said current/voltage converter comprises a first and second output transistors connected in series between the bit line and said first voltage source, one of said first and second output transistors being a P type transistor and the other one being an N type transistor, the gate of one of said first and second output transistors being connected to the output of said servo-control circuit, the gate of the other of said first and second output transistors being connected to the common node of said first and second output transistors.

Claim 10

Dependent Claim 80 words

In an integrated memory circuit, a method for pre-charging a pre-charging node on a bit line comprising the steps of: applying a first output voltage from a servo-control circuit to a driving circuit for rapidly charging said pre-charging node toward a first voltage value; and applying a second output voltage from said servo-control circuit to said driving circuit for maintaining said pre-charging node at a desired voltage value, wherein said first voltage value is greater than said desired voltage value.

Claim 11

Dependent Claim 80 words

In an integrated memory circuit, a method for pre-charging a pre-charging node on a bit line comprising the steps of: applying a first output voltage from a servo-control circuit to a driving circuit for rapidly charging said pre-charging node toward a first voltage value; and applying a second output voltage from said servo-control circuit to said driving circuit for maintaining said pre-charging node at a desired voltage value, wherein said first voltage value is greater than said desired voltage value.

Claim 12

Dependent Claim 19 words

The method for pre-charging a pre-charging node according to claim 9 wherein said driving circuit is a pre-charging transistor.

Claim 13

Dependent Claim 33 words

The pre-charging method according to claim 9 wherein said servo-control circuit is switched from said first output voltage to said second output voltage when said pre-charging node has substantially attained desired voltage value.

Claim 14

Dependent Claim 15 words

The pre-charging method according to claim 11 wherein said driving circuit is a pre-charging transistor.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1996-11-01	1997-05-03	1997-11-02	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2000-11-01	2001-05-03	2001-11-02	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2004-11-01	2005-05-03	2005-11-02	$7700.00	Window Closed / Lapsed

Pre-charging method for the reading of memories

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