Patent US5264723A successfully refreshed from Google Patents.
US5264723A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with MOS capacitor for improved ESD protection
Assignee: Nokia Bell Labs
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Filing: 1992-04-09
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Granted: 1993-11-23
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Expires: 2012-04-09
Abstract
Abstract A MOS capacitor, with the polysilicon gate level as one plate, the gate oxide as the insulator, and the underlying semiconductor tub region as the other plate, is used to increase electrostatic discharge (ESD) protection. In an illustrative embodiment, wherein the substrate is n-type and the tub is p-type, the polysilicon level is connected to the negative power supply voltage conductor (V SS ), and the underlying semiconductor region is connected to the positive power supply conductor (V DD ). Since the tub region is p-type, an accumulation-type capacitor is formed. Surprisingly, the thin gate oxide is sufficient to withstand the high ESD voltages, with the protection increasing in one design from less than 1000 volts without the capacitor to 2000 volts with the capacitor.
Inventors
- 👤 Mark S. Strauss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:57
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10P; H10P14/00; H10P14/40; H10P14/416; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/038; H10W20/046
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
141 words
An integrated circuit formed in a semiconductor substrate and including a bondpad coupled to at least one of input or output circuitry, and further including positive and negative power supply voltage conductors, characterized in that said integrated circuit further comprises an accumulation-type capacitor having: a first capacitor plate formed in a doped tub region of a first conductivity type formed in said substrate of a second conductivity type, with said first capacitor plate being connected to a first one of said power supply voltage conductors; and with said substrate also being connected to said first one of said power supply voltage conductors; and a second capacitor plate formed in a deposited conductive layer overlying said doped tub region, and separated therefrom by a dielectric region, with said second capacitor plate connected to a second one of said power supply voltage conductors.
Claim 2
Dependent Claim
141 words
An integrated circuit formed in a semiconductor substrate and including a bondpad coupled to at least one of input or output circuitry, and further including positive and negative power supply voltage conductors, characterized in that said integrated circuit further comprises an accumulation-type capacitor having: a first capacitor plate formed in a doped tub region of a first conductivity type formed in said substrate of a second conductivity type, with said first capacitor plate being connected to a first one of said power supply voltage conductors; and with said substrate also being connected to said first one of said power supply voltage conductors; and a second capacitor plate formed in a deposited conductive layer overlying said doped tub region, and separated therefrom by a dielectric region, with said second capacitor plate connected to a second one of said power supply voltage conductors.
Claim 3
Dependent Claim
46 words
The integrated circuit of claim 1 further comprising a conduction device connected between said bondpad and said positive power supply conductor for conducting electrical current resulting from a positive ESD voltage on said bondpad to the capacitor plate connected to said positive power supply voltage conductor.
Claim 4
Dependent Claim
32 words
The integrated circuit of claim 2 wherein said conduction device is a diode having a p+ region connected to said bondpad, and an n region connected to said positive power supply conductor.
Claim 5
Dependent Claim
48 words
The integrated circuit of claim 2 wherein said conduction device is a p-channel field effect transistor having a p+ drain region connected to said bondpad, and having a n-tub region in which said drain is formed, with said n-tub region being connected to said positive power supply conductor.
Claim 6
Dependent Claim
17 words
The integrated circuit of claim 1 wherein said capacitor has a capacitance of at least 100 picofarads.
Claim 7
Dependent Claim
18 words
The integrated circuit of claim 1 wherein said dielectric region has a thickness of less than 25 nanometers.
Claim 8
Dependent Claim
25 words
The integrated circuit of claim 1 wherein said dielectric region is formed in the same dielectric layer as the gate dielectric in said integrated circuit.
Claim 9
Dependent Claim
23 words
The integrated circuit of claim 1 wherein said deposited conductive layer is the same layer as forms gate electrodes in said integrated circuit.
Claim 10
Dependent Claim
14 words
The integrated circuit of claim 8 wherein said deposited conductive layer comprises doped polysilicon.
Claim 11
Dependent Claim
16 words
The integrated circuit of claim 9 wherein said deposited conductive layer further comprises a metal silicide.
Claim 12
Dependent Claim
70 words
The integrated circuit of claim 1 wherein said first conductivity type is p-type, said second conductivity type is n-type, said first one of said power supply voltage conductors is the positive voltage conductor, and said second one of said power supply voltage conductors is the negative voltage conductor; and wherein said substrate is connected to said positive voltage conductor by means of an n+ doped region formed in said substrate.
Claim 13
Dependent Claim
70 words
The integrated circuit of claim 1 wherein said first conductivity type is n-type, said second conductivity type is p-type, said first one of said power supply voltage conductors is the negative voltage conductor, and said second one of said power supply voltage conductors is the positive voltage conductor; and wherein said substrate is connected to said negative voltage conductor by means of a p+ doped region formed in said substrate.
Claim 14
Dependent Claim
145 words
An integrated circuit formed in a n-type semiconductor substrate and including a bondpad coupled to at least one of input or output circuitry, and further including positive and negative power supply voltage conductors, characterized in that said integrated circuit further comprises an accumulation-type capacitor having: a first capacitor plate formed in a p-type doped tub region formed in said n-type substrate, with said first capacitor plate being connected to said positive power supply voltage conductor; and with said substrate also being connected to said positive power supply voltage conductor; and a second capacitor plate overlying said p-type doped tub region and comprising deposited polysilicon formed in the same layer that forms gate electrodes in said integrated circuit, and with said second capacitor plate being connected to said negative power supply voltage conductor; and wherein the capacitor plates are separated by a gate oxide dielectric region.
Claim 15
Dependent Claim
145 words
An integrated circuit formed in a n-type semiconductor substrate and including a bondpad coupled to at least one of input or output circuitry, and further including positive and negative power supply voltage conductors, characterized in that said integrated circuit further comprises an accumulation-type capacitor having: a first capacitor plate formed in a p-type doped tub region formed in said n-type substrate, with said first capacitor plate being connected to said positive power supply voltage conductor; and with said substrate also being connected to said positive power supply voltage conductor; and a second capacitor plate overlying said p-type doped tub region and comprising deposited polysilicon formed in the same layer that forms gate electrodes in said integrated circuit, and with said second capacitor plate being connected to said negative power supply voltage conductor; and wherein the capacitor plates are separated by a gate oxide dielectric region.
Claim 16
Dependent Claim
39 words
The integrated circuit of claim 13 further comprising a conduction device connected between said bondpad and said positive power supply conductor for conducting electrical current resulting from a positive ESD voltage on said bondpad to said first capacitor plate.
Claim 17
Dependent Claim
32 words
The integrated circuit of claim 14 wherein said conduction device is a diode having a p+ region connected to said bondpad, and an n region connected to said positive power supply conductor.
Claim 18
Dependent Claim
48 words
The integrated circuit of claim 14 wherein said conduction device is a p-channel field effect transistor having a p+ drain region connected to said bondpad, and having a n-tub region in which said drain is formed, with said n-tub region being connected to said positive power supply conductor.
Claim 19
Dependent Claim
17 words
The integrated circuit of claim 13 wherein said capacitor has a capacitance of at least 100 picofarads.
Claim 20
Dependent Claim
18 words
The integrated circuit of claim 13 wherein said dielectric region has a thickness of less than 25 nanometers.
Claim 21
Dependent Claim
145 words
An integrated circuit formed in a p-type semiconductor substrate and including a bondpad coupled to at least one of input or output circuitry, and further including positive and negative power supply voltage conductors, characterized in that said integrated circuit further comprises an accumulation-type capacitor having: a first capacitor plate formed in a n-type doped tub region formed in said p-type substrate, with said first capacitor plate being connected to said negative power supply voltage conductor; and with said substrate also being connected to said negative power supply voltage conductor; and a second capacitor plate overlying said n-type doped tub region and comprising deposited polysilicon formed in the same layer that forms gate electrodes in said integrated circuit, and with said second capacitor plate being connected to said positive power supply voltage conductor; and wherein the capacitor plates are separated by a gate oxide dielectric region.
Claim 22
Dependent Claim
145 words
An integrated circuit formed in a p-type semiconductor substrate and including a bondpad coupled to at least one of input or output circuitry, and further including positive and negative power supply voltage conductors, characterized in that said integrated circuit further comprises an accumulation-type capacitor having: a first capacitor plate formed in a n-type doped tub region formed in said p-type substrate, with said first capacitor plate being connected to said negative power supply voltage conductor; and with said substrate also being connected to said negative power supply voltage conductor; and a second capacitor plate overlying said n-type doped tub region and comprising deposited polysilicon formed in the same layer that forms gate electrodes in said integrated circuit, and with said second capacitor plate being connected to said positive power supply voltage conductor; and wherein the capacitor plates are separated by a gate oxide dielectric region.
Claim 23
Dependent Claim
39 words
The integrated circuit of claim 19 further comprising a conduction device connected between said bondpad and said positive power supply conductor for conducting electrical current resulting from a positive ESD voltage on said bondpad to said second capacitor plate.
Claim 24
Dependent Claim
32 words
The integrated circuit of claim 20 wherein said conduction device is a diode having a p+ region connected to said bondpad, and an n region connected to said positive power supply conductor.
Claim 25
Dependent Claim
48 words
The integrated circuit of claim 20 wherein said conduction device is a p-channel field effect transistor having a p+ drain region connected to said bondpad, and having a n-tub region in which said drain is formed, with said n-tub region being connected to said positive power supply conductor.
Claim 26
Dependent Claim
17 words
The integrated circuit of claim 19 wherein said capacitor has a capacitance of at least 100 picofarads.
Claim 27
Dependent Claim
18 words
The integrated circuit of claim 19 wherein said dielectric region has a thickness of less than 25 nanometers.
Claim 28
Dependent Claim
48 words
The integrated circuit of claim 1 further comprising a field oxide isolation region formed on the surface of said doped tub region and surrounding a central portion of said second capacitor plate, and wherein the edge of said second capacitor plate extends over said field oxide isolation region.
Claim 29
Dependent Claim
48 words
The integrated circuit of claim 13 further comprising a field oxide isolation region formed on the surface of said doped tub region and surrounding a central portion of said second capacitor plate, and wherein the edge of said second capacitor plate extends over said field oxide isolation region.
Claim 30
Dependent Claim
48 words
The integrated circuit of claim 19 further comprising a field oxide isolation region formed on the surface of said doped tub region and surrounding a central portion of said second capacitor plate, and wherein the edge of said second capacitor plate extends over said field oxide isolation region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-22 | 1997-05-24 | 1997-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-22 | 2001-05-24 | 2001-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-22 | 2005-05-24 | 2005-11-23 | $7700.00 | Window Closed / Lapsed |