Flash eprom memory circuit having source side programming

Claim 1

A flash EPROM memory array comprising a plurality of memory cells arranged in a matrix of rows and columns, each memory cell including a portion of a semiconductor substrate of a first conductivity type, a source region and a drain region of a second conductivity type formed in spaced alignment in said substrate with a channel region therebetween, a first gate insulation formed on a major surface of said substrate, A floating gate electrode formed on said first gate insulation and partially overlapping said channel region, a second gate insulation formed on said floating gate, a control gate formed on said second gate insulation and overlapping said floating gate electrode, said drain region being self-aligned with said floating gate and said control gate with said source region being laterally spaced from said floating gate, a third insulation layer formed over said control gate electrode, said floating gate electrode and said channel region; a select gate electrode formed on said third insulation layer and over said channel region abutting said source region, said control gate electrode extending from said cell in one direction to adjacent cells in a column, said select gate electrode extending over said drain region, said source region, and said control gate electrode and from said cell in a direction perpendicular to said one direction to adjacent cells in a row, means connecting said drain regions of memory cells in columns, means connecting said source regions of memory cells in columns, means connecting said control gate electrodes of memory cells in columns, and means connecting said select gate electrodes of memory cells in rows perpendicular to said columns wherein programming of a cell is by charge injection from a source region into a floating gate and erasure of a programmed cell is by charge transfer from a floating gate to a drain region.