High density EEPROM cell with tunnel oxide stripe

Claim 1

A method of fabricating an electrically-erasable programmable read only memory (EEPROM) cell formed in semiconductor material of P-type conductivity, the method comprising: (a) forming first and second spaced-apart first field oxide (FOX1) regions in the P-type semiconductor material to define a P-type active device region therebetween; (b) forming first and second spaced-apart bit lines of N-type conductivity in the P-type semiconductor material adjacent to the first and second FOX1 regions, respectively, such that the first and second bit lines define a P-type channel region therebetween; (c) forming first and second spaced-apart second field oxide (FOX2) regions adjacent to the first and second FOX1 regions, respectively, and overlying the first and second bit lines, respectively; (d) forming a layer of gate dielectric material on the P-type semiconductor material between the first and second FOX2 regions; (e) defining a tunnel stripe in the gate dielectric material and growing tunnel dielectric material in the tunnel stripe such that the thickness of the tunnel dielectric stripe is less than the thickness of the gate dielectric material; (f) forming a layer of first conductive material over the gate dielectric material and the dielectric tunnel stripe to define a floating gate of the EEPROM cell; (g) forming a layer of intermediate dielectric material over the floating gate; and (h) forming a layer of second conductive material over the layer of intermediate dielectric material to define a control gate of the EEPROM cell, the dielectric tunnel stripe extending across a plurality of EEPROM cells sharing a first and second bit lines, the tunneling region of each such EEPROM cell being defined by the intersection of the dielectric tunnel stripe and the floating gate of each such EEPROM cell.

Claim 2

A method of fabricating an electrically-erasable programmable read only memory (EEPROM) cell formed in semiconductor material of P-type conductivity, the method comprising: (a) forming first and second spaced-apart first field oxide (FOX1) regions in the P-type semiconductor material to define a P-type active device region therebetween; (b) forming first and second spaced-apart bit lines of N-type conductivity in the P-type semiconductor material adjacent to the first and second FOX1 regions, respectively, such that the first and second bit lines define a P-type channel region therebetween; (c) forming first and second spaced-apart second field oxide (FOX2) regions adjacent to the first and second FOX1 regions, respectively, and overlying the first and second bit lines, respectively; (d) forming a layer of gate dielectric material on the P-type semiconductor material between the first and second FOX2 regions; (e) defining a tunnel stripe in the gate dielectric material and growing tunnel dielectric material in the tunnel stripe such that the thickness of the tunnel dielectric stripe is less than the thickness of the gate dielectric material; (f) forming a layer of first conductive material over the gate dielectric material and the dielectric tunnel stripe to define a floating gate of the EEPROM cell; (g) forming a layer of intermediate dielectric material over the floating gate; and (h) forming a layer of second conductive material over the layer of intermediate dielectric material to define a control gate of the EEPROM cell, the dielectric tunnel stripe extending across a plurality of EEPROM cells sharing a first and second bit lines, the tunneling region of each such EEPROM cell being defined by the intersection of the dielectric tunnel stripe and the floating gate of each such EEPROM cell.