Patent US5329486A successfully refreshed from Google Patents.
US5329486A
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Ferromagnetic memory device
Assignee: Apple Inc
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Filing: 1993-07-23
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Granted: 1994-07-12
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Expires: 2013-07-23
Abstract
Abstract A ferromagnetic memory circuit (10) and a ferromagnetic memory device (15) which has a substrate (42). Within the substrate (42), a first current electrode (44) and a second current electrode (46) are formed. A control electrode (50) is formed to control current flow between the first and second current electrodes (44 and 46). A ferromagnetic region (68) is used to store a logic value via magnetic flux. Two conductive layers (62 and 70) and a conductive spacer (78) form a sense conductor for device (15). The sense conductor is used to externally provide the logic value stored in the device (15). A conductive layer (82) forms a program/erase line for altering the logic value stored in the device (15). A logic one or a logic zero is stored in ferromagnetic region (68) depending upon a direction and a magnitude of current flow through conductive layer (82).
Inventors
- 👤 Craig S. Lage
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:43
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/06; G11C11/06007; G11C11/06014; G11C11/06021; G11C11/06028; G11C11/06035; G11C11/06042
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
97 words
A ferromagnetic memory circuit comprising: a transistor having a first current electrode, a second current electrode for receiving a power supply voltage, and a control electrode; a ferromagnetic core positioned in close proximity to the transistor wherein the ferromagnetic core and the transistor are formed overlying a same substrate material; a power supply line conductor coupled to the second current electrode of the transistor; a bit line conductor passing through the ferromagnetic core and being coupled to the first current electrode of said transistor; and a word line conductor coupled to the control electrode of the transistor.
Claim 2
Dependent Claim
97 words
A ferromagnetic memory circuit comprising: a transistor having a first current electrode, a second current electrode for receiving a power supply voltage, and a control electrode; a ferromagnetic core positioned in close proximity to the transistor wherein the ferromagnetic core and the transistor are formed overlying a same substrate material; a power supply line conductor coupled to the second current electrode of the transistor; a bit line conductor passing through the ferromagnetic core and being coupled to the first current electrode of said transistor; and a word line conductor coupled to the control electrode of the transistor.
Claim 3
Dependent Claim
22 words
The circuit of claim 1 further comprising: a sense line conductor formed through the ferromagnetic core and isolated from the bit line.
Claim 4
Dependent Claim
34 words
The circuit of claim 1 wherein the transistor is a bipolar transistor and the first current electrode is an emitter, the second current electrode is a collector, and the control electrode is a base.
Claim 5
Dependent Claim
44 words
The circuit of claim 1 wherein the transistor is a field effect transistor wherein the first current electrode and the second current electrode are respectively either a source and a drain or a drain and a source, and the control electrode is a gate.
Claim 6
Dependent Claim
122 words
A ferromagnetic memory cell comprising: a substrate having a surface; a transistor having a first current electrode formed within the substrate and exposed at the surface of the substrate, a second current electrode formed within the substrate and exposed at the surface of the substrate, and a control electrode which lies substantially between the first current electrode and the second current electrode and controls current flow between the first current electrode and the second current electrode; a ferromagnetic region overlying the substrate and positioned in close proximity to the transistor; an opening formed in the ferromagnetic region; and a first conductive region formed within the opening in the ferromagnetic region, the first conductive region being electrically coupled to the first current electrode.
Claim 7
Dependent Claim
122 words
A ferromagnetic memory cell comprising: a substrate having a surface; a transistor having a first current electrode formed within the substrate and exposed at the surface of the substrate, a second current electrode formed within the substrate and exposed at the surface of the substrate, and a control electrode which lies substantially between the first current electrode and the second current electrode and controls current flow between the first current electrode and the second current electrode; a ferromagnetic region overlying the substrate and positioned in close proximity to the transistor; an opening formed in the ferromagnetic region; and a first conductive region formed within the opening in the ferromagnetic region, the first conductive region being electrically coupled to the first current electrode.
Claim 8
Dependent Claim
35 words
The memory cell of claim 5 wherein the transistor is a bipolar transistor and the first current electrode is an emitter, the second current electrode is a collector, and the control electrode is a base.
Claim 9
Dependent Claim
45 words
The memory cell of claim 5 wherein the transistor is a field effect transistor wherein the first current electrode and the second current electrode are respectively either a source and a drain or a drain and a source, and the control electrode is a gate.
Claim 10
Dependent Claim
36 words
The memory cell of claim 5 wherein the first conductive region is formed as a bit line conductor and is used for erasing and programming the ferromagnetic region, and the first conductive region has a periphery.
Claim 11
Dependent Claim
53 words
The memory cell of claim 8 further comprising: a second conductive region formed laterally adjacent and around the periphery of the first conductive region, the second conductive region being adjacent the opening in the ferromagnetic region and functioning as a sense line for externally providing a logic value stored by the ferromagnetic region.
Claim 12
Dependent Claim
17 words
The memory cell of claim 9 wherein the second conductive region is formed as a sidewall spacer.
Claim 13
Dependent Claim
35 words
The memory cell of claim 9 wherein the second conductive region further comprises: a sidewall dielectric region which is formed laterally adjacent the ferromagnetic region and isolates the second conductive region from the ferromagnetic region.
Claim 14
Dependent Claim
77 words
An integrated circuit having a plurality of memory cells, each memory cell within the plurality of memory cells comprising: a substrate portion; a transistor having an electrode overlying the substrate portion; a conductive element connected to the electrode, the conductive element overlying the substrate portion; and a ferromagnetic core coupled to the conductive element wherein the magnetic energy in the ferromagnetic core is changed by current through the ferromagnetic core, the ferromagnetic core overlying the substrate portion.
Claim 15
Dependent Claim
77 words
An integrated circuit having a plurality of memory cells, each memory cell within the plurality of memory cells comprising: a substrate portion; a transistor having an electrode overlying the substrate portion; a conductive element connected to the electrode, the conductive element overlying the substrate portion; and a ferromagnetic core coupled to the conductive element wherein the magnetic energy in the ferromagnetic core is changed by current through the ferromagnetic core, the ferromagnetic core overlying the substrate portion.
Claim 16
Dependent Claim
16 words
The integrated circuit of claim 12 wherein the transistor is a metal oxide semiconductor (MOS) transistor.
Claim 17
Dependent Claim
80 words
A memory cell comprising: a transistor having an electrode; a dielectric layer overlying the transistor and having an opening which exposes the electrode; a conductive element connected to the electrode; and a ferromagnetic core formed in close proximity to the conductive element so that the ferromagnetic core is electrically coupled to the conductive element wherein the magnetic energy in the ferromagnetic core is selectively changed by a current flowing through the conductive element, the ferromagnetic core overlying the dielectric layer.
Claim 18
Dependent Claim
80 words
A memory cell comprising: a transistor having an electrode; a dielectric layer overlying the transistor and having an opening which exposes the electrode; a conductive element connected to the electrode; and a ferromagnetic core formed in close proximity to the conductive element so that the ferromagnetic core is electrically coupled to the conductive element wherein the magnetic energy in the ferromagnetic core is selectively changed by a current flowing through the conductive element, the ferromagnetic core overlying the dielectric layer.
Claim 19
Dependent Claim
16 words
The memory cell of claim 14 wherein the transistor is a metal oxide semiconductor (MOS) transistor.
Claim 20
Dependent Claim
39 words
An integrated circuit memory cell comprising: a semiconductor substrate; a transistor device formed within the semiconductor substrate; a dielectric layer overlying the transistor device; an annular ferromagnetic core overlying the dielectric layer and being coupled to the transistor device.
Claim 21
Dependent Claim
39 words
An integrated circuit memory cell comprising: a semiconductor substrate; a transistor device formed within the semiconductor substrate; a dielectric layer overlying the transistor device; an annular ferromagnetic core overlying the dielectric layer and being coupled to the transistor device.
Claim 22
Dependent Claim
40 words
The integrated circuit memory cell of claim 16 further comprising: a conductor connected to the transistor device and positioned in close proximity to the annular ferromagnetic core, current through the conductor affecting magnetic energy stored in the annular ferromagnetic core.
Claim 23
Dependent Claim
31 words
The integrated circuit memory cell of claim 16 wherein the annular ferromagnetic core contains a value selected from a group consisting of: a logic high value and a logic low value.
Claim 24
Dependent Claim
84 words
A ferromagnetic memory circuit comprising: a power supply conductor; a transistor having a first current electrode, a second current electrode for receiving a power supply voltage from the power supply conductor, and a control electrode; a ferromagnetic core formed directly overlying a portion of the transistor and being encapsulated in a dielectric layer; and a conductor passing adjacent to the ferromagnetic core and being coupled to the first current electrode of said transistor, the conductor selectively affecting a magnetic field within the ferromagnetic core.
Claim 25
Dependent Claim
84 words
A ferromagnetic memory circuit comprising: a power supply conductor; a transistor having a first current electrode, a second current electrode for receiving a power supply voltage from the power supply conductor, and a control electrode; a ferromagnetic core formed directly overlying a portion of the transistor and being encapsulated in a dielectric layer; and a conductor passing adjacent to the ferromagnetic core and being coupled to the first current electrode of said transistor, the conductor selectively affecting a magnetic field within the ferromagnetic core.
Claim 26
Dependent Claim
86 words
A ferromagnetic memory cell comprising: a transistor having a first current electrode, a second current electrode, and a control electrode which lies substantially between the first current electrode and the second current electrode and controls current flow between the first current electrode and the second current electrode; a ferromagnetic region positioned adjacent the transistor and being at least partially surrounded by a dielectric layer; and a first conductive region formed adjacent the ferromagnetic region, the first conductive region being electrically coupled to the first current electrode.
Claim 27
Dependent Claim
86 words
A ferromagnetic memory cell comprising: a transistor having a first current electrode, a second current electrode, and a control electrode which lies substantially between the first current electrode and the second current electrode and controls current flow between the first current electrode and the second current electrode; a ferromagnetic region positioned adjacent the transistor and being at least partially surrounded by a dielectric layer; and a first conductive region formed adjacent the ferromagnetic region, the first conductive region being electrically coupled to the first current electrode.
Claim 28
Dependent Claim
86 words
An integrated circuit wherein the integrated circuit has a plurality of magnetic memory devices formed on a substrate, one magnetic memory device comprising: only one single transistor; a ferromagnetic core in close proximity to the only one single transistor; a conductor coupled to the transistor and being positioned close enough to the ferromagnetic core to allow the ferromagnetic core to store a logic value selected from a group consisting of: a logic one and a logic zero, in response to a current flow through the conductor.
Claim 29
Dependent Claim
86 words
An integrated circuit wherein the integrated circuit has a plurality of magnetic memory devices formed on a substrate, one magnetic memory device comprising: only one single transistor; a ferromagnetic core in close proximity to the only one single transistor; a conductor coupled to the transistor and being positioned close enough to the ferromagnetic core to allow the ferromagnetic core to store a logic value selected from a group consisting of: a logic one and a logic zero, in response to a current flow through the conductor.
Claim 30
Dependent Claim
96 words
A semiconductor magnetic memory device comprising: a substrate; a transistor formed from the substrate and having a first current electrode overlying the substrate, a second current electrode overlying the substrate and being separated from the first current electrode by a channel region, and a gate electrode which overlies the channel region; a first dielectric layer formed overlying the transistor; a ferromagnetic region formed overlying the first dielectric layer, the ferromagnetic region having a sidewall; a second dielectric layer formed overlying the ferromagnetic region; and a first conductive region formed adjacent the sidewall of the ferromagnetic region.
Claim 31
Dependent Claim
96 words
A semiconductor magnetic memory device comprising: a substrate; a transistor formed from the substrate and having a first current electrode overlying the substrate, a second current electrode overlying the substrate and being separated from the first current electrode by a channel region, and a gate electrode which overlies the channel region; a first dielectric layer formed overlying the transistor; a ferromagnetic region formed overlying the first dielectric layer, the ferromagnetic region having a sidewall; a second dielectric layer formed overlying the ferromagnetic region; and a first conductive region formed adjacent the sidewall of the ferromagnetic region.
Claim 32
Dependent Claim
23 words
The semiconductor magnetic memory device of claim 22 wherein a dielectric sidewall spacer is formed laterally adjacent the sidewall of the ferromagnetic region.
Claim 33
Dependent Claim
20 words
The semiconductor magnetic memory device of claim 22 wherein a second conductive region is formed adjacent the first conductive region.
References Cited (Backward Citations)
US3155948A
Cited
US3419855A
Cited
US3753485A
Cited
US4103340A
Cited
US4887236A
Cited
US4831427A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |