US5329487A
Expired / Lapsed
US
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Two transistor flash EPROM cell
Assignee: Altera Corp
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Filing: 1993-03-08
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Granted: 1994-07-12
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Expires: 2013-03-08
Abstract
Abstract A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by overerasure (negative voltage threshold) of the floating gate transistor.
Inventors
- 👤 Anil Gupta
- 👤 Kuo-Lung Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:32
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/0425; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
93 words
A memory cell comprising: a word line; a write line; a read line; a first transistor having a gate connected to the word line, a drain to the write line, a source, and a floating gate; and a second transistor having a gate connected to the word line, a drain connected to the read line, a source and a floating gate connected to the floating gate of the first transistor, wherein the floating gate of the second transistor does not extend to either of the source and the drain of the second transistor.
Claim 2
Dependent Claim
93 words
A memory cell comprising: a word line; a write line; a read line; a first transistor having a gate connected to the word line, a drain to the write line, a source, and a floating gate; and a second transistor having a gate connected to the word line, a drain connected to the read line, a source and a floating gate connected to the floating gate of the first transistor, wherein the floating gate of the second transistor does not extend to either of the source and the drain of the second transistor.
Claim 3
Dependent Claim
22 words
A cell as in claim 1 wherein the source of the second transistor is connected to the source of the first transistor.
Claim 4
Dependent Claim
14 words
A cell as in claim 1 wherein the second transistor comprises a merged transistor.
Claim 5
Dependent Claim
20 words
A cell as in claim 3 wherein the merged transistor includes a floating gate transistor and a field effect transistor.
Claim 6
Dependent Claim
16 words
A cell as in claim 4 wherein the field effect transistor comprises an enhancement type transistor.
Claim 7
Dependent Claim
26 words
A memory cell as in claim 1 wherein the first transistor has a threshold voltage which is different from a threshold voltage of the second transistor.
Claim 8
Dependent Claim
14 words
A plurality of memory cells as in claim 1 interconnected to form an array.
Claim 9
Dependent Claim
45 words
An array as in claim 7 wherein: the sources of the groups of the first transistors are connected together to a node; and an additional transistor is coupled to the node and to a potential source to switchably connect the node to the potential source.
Claim 10
Dependent Claim
105 words
In a flash electrically erasable programmable read only memory having word lines, write lines, read lines, and source lines, and having two-transistor memory cells with a merged transistor having a gate symmetrically aligned with a floating gate, a method of storing data in a selected memory cell comprising contemporaneously: applying a first high potential to a write line coupled to the selected cell; applying a second high potential to a word line coupled to the selected cell; applying first low voltage to a read line coupled to the selected cell; and applying a second low voltage to a source line coupled to the selected cell.
Claim 11
Dependent Claim
105 words
In a flash electrically erasable programmable read only memory having word lines, write lines, read lines, and source lines, and having two-transistor memory cells with a merged transistor having a gate symmetrically aligned with a floating gate, a method of storing data in a selected memory cell comprising contemporaneously: applying a first high potential to a write line coupled to the selected cell; applying a second high potential to a word line coupled to the selected cell; applying first low voltage to a read line coupled to the selected cell; and applying a second low voltage to a source line coupled to the selected cell.
Claim 12
Dependent Claim
54 words
A method as in claim 9 further comprising reading the stored data from the selected cell by contemporaneously: applying a logical one voltage level to the word line coupled to the selected cell; applying a low voltage to the source line; and detecting the potential of the read line coupled to the selected cell.
Claim 13
Dependent Claim
82 words
A nonvolatile memory cell less susceptible to overerasure comprising: a first transistor having a gate, a floating gate, a source and a drain; a second transistor having a gate connected to the gate of the first transistor, a floating gate connected to the floating gate of the first transistor, a source connected to the source of the first transistor, and a drain; and wherein the floating gate of the second transistor does not extend to either of the source and the drain.
Claim 14
Dependent Claim
82 words
A nonvolatile memory cell less susceptible to overerasure comprising: a first transistor having a gate, a floating gate, a source and a drain; a second transistor having a gate connected to the gate of the first transistor, a floating gate connected to the floating gate of the first transistor, a source connected to the source of the first transistor, and a drain; and wherein the floating gate of the second transistor does not extend to either of the source and the drain.
Claim 15
Dependent Claim
25 words
The nonvolatile memory cell of claim 11 wherein the floating gate of the second transistor is symmetrically aligned with the gate of the second transistor.
References Cited (Backward Citations)
US4403307A
Cited
US5220533A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |