US5331594A
Expired / Lapsed
US
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Semiconductor memory device having word line and bit line test circuits
Assignee: Samsung Electronics Co Ltd
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Filing: 1991-10-10
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Granted: 1994-07-19
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Expires: 2011-10-10
Abstract
Abstract A semiconductor memory device such as a ROM is provided with a word line test circuit and a word line drive circuit. The word line test circuit outputs a high level signal when a test signal is applied and a low level signal when the test signal is not applied. The word line drive circuit drives the respective word lines in the memory cell array, and is connected to the output of the word line test circuit, so that when driving one group of word lines (either the odd-numbered word lines or the even-numbered word lines), a high level signal is applied to the one group of word lines, and when not driving the one group of word lines, a low level signal is applied to the one group of word lines. On the other hand, when driving the other group of word lines, a high level signal is applied to the other group of word lines, and when not driving the other group of word lines, the output signal from the word line test circuit is applied to the other group of word lines, thereby enabling short circuits between adjacent word lines to be identified quickly. A bit line test switch circuit is provided which is connected to the bit lines in the memory cell array. In response to a test signal, the bit line test switch circuit applies signals of different levels to the odd-numbered and even-numbered bit lines respectively, and short circuits between adjacent bit lines can be identified quickly.
Inventors
- 👤 Yasuhiro Hotta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:35
CPC Classifications
G; G11; G11C; G11C16/00; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/50
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
115 words
In a semiconductor memory device comprising a plurality of word lines which are arranged in parallel, and word line drive means for respectively driving said word lines, said semiconductor memory device further comprises word line test means for receiving a test signal, and for producing an output signal, the voltage level of said output signal being a first level when said test signal is active and a second level when said test signal is not active, preselected ones of said word line drive means being coupled to an output of said test means such that when the preselected word line drive means are not active, said output signal is applied to said preselected word lines.
Claim 2
Dependent Claim
115 words
In a semiconductor memory device comprising a plurality of word lines which are arranged in parallel, and word line drive means for respectively driving said word lines, said semiconductor memory device further comprises word line test means for receiving a test signal, and for producing an output signal, the voltage level of said output signal being a first level when said test signal is active and a second level when said test signal is not active, preselected ones of said word line drive means being coupled to an output of said test means such that when the preselected word line drive means are not active, said output signal is applied to said preselected word lines.
Claim 3
Dependent Claim
22 words
A semiconductor memory device according to claim 1, wherein said preselected word line drive means are ones connected to odd-numbered word lines.
Claim 4
Dependent Claim
22 words
A semiconductor memory device according to claim 1, wherein said preselected word line drive means are ones connected to even-numbered word lines.
Claim 5
Dependent Claim
193 words
In a semiconductor memory device comprising a plurality of word lines which are arranged in parallel, a plurality of bit lines which are arranged in parallel, and word line drive means for respectively driving said word lines, said semiconductor memory device further comprises: word line test means for receiving a test signal, and for producing an output signal, the voltage level of said output signal being a first level when said test signal is active and a second level when said test signal is not active, said first and second levels being different from each other; and bit line test means for receiving a test signal, and for, when said test signal is active, applying a third output signal to odd-numbered ones of said bit lines and a fourth output signal to even-numbered ones of said bit lines, said third and fourth output signals being different in voltage level from each other, preselected ones of said word line drive means being coupled to an output of said word line test means such that when the preselected word line drive means are not active, said output signal is applied to said preselected word lines.
Claim 6
Dependent Claim
193 words
In a semiconductor memory device comprising a plurality of word lines which are arranged in parallel, a plurality of bit lines which are arranged in parallel, and word line drive means for respectively driving said word lines, said semiconductor memory device further comprises: word line test means for receiving a test signal, and for producing an output signal, the voltage level of said output signal being a first level when said test signal is active and a second level when said test signal is not active, said first and second levels being different from each other; and bit line test means for receiving a test signal, and for, when said test signal is active, applying a third output signal to odd-numbered ones of said bit lines and a fourth output signal to even-numbered ones of said bit lines, said third and fourth output signals being different in voltage level from each other, preselected ones of said word line drive means being coupled to an output of said word line test means such that when the preselected word line drive means are not active, said output signal is applied to said preselected word lines.
Claim 7
Dependent Claim
22 words
A semiconductor memory device according to claim 4, wherein said preselected word line drive means are ones connected to odd-numbered word lines.
Claim 8
Dependent Claim
22 words
A semiconductor memory device according to claim 4, wherein said preselected word line drive means are ones connected to even-numbered word lines.
Claim 9
Dependent Claim
36 words
A semiconductor memory device according to claim 4, wherein said bit line test means comprises switch means for, when said test signal is active, connecting all of said bit line test means to said bit lines.
Claim 10
Dependent Claim
36 words
A semiconductor memory device according to claim 1 wherein said word line test means detects short circuits between adjacent word lines by applying voltage across adjacent word lines and detecting current flow through said test means.
Claim 11
Dependent Claim
105 words
A semiconductor memory device comprising a plurality of bit lines which are arranged in parallel, said semiconductor memory device further comprises a bit line test means for receiving a test signal, and for, when said test signal is active, applying a first output signal to odd-numbered ones of said bit lines and a second output signal to even-numbered ones of said bit lines, and first and second output signals being different in voltage level from each other wherein said bit line test means detects short circuits between adjacent bit lines by applying a voltage across adjacent bitlines and detecting current flow through said test means.
Claim 12
Dependent Claim
105 words
A semiconductor memory device comprising a plurality of bit lines which are arranged in parallel, said semiconductor memory device further comprises a bit line test means for receiving a test signal, and for, when said test signal is active, applying a first output signal to odd-numbered ones of said bit lines and a second output signal to even-numbered ones of said bit lines, and first and second output signals being different in voltage level from each other wherein said bit line test means detects short circuits between adjacent bit lines by applying a voltage across adjacent bitlines and detecting current flow through said test means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-18 | 1998-01-17 | 1998-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-18 | 2002-01-17 | 2002-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-18 | 2006-01-17 | 2006-07-19 | $7700.00 | Window Closed / Lapsed |