US5333016A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Image display apparatus
Assignee: Rohm Co Ltd
•
Filing: 1992-06-05
•
Granted: 1994-07-26
•
Expires: 2012-06-05
Abstract
Abstract An image display apparatus for determining a vertical display position according to the count given by a vertical address counter causes a circuit for counting horizontal synchronizing signals to be started according to a vertical synchronizing signal on receiving vertical and horizontal synchronizing signals, and resets the vertical address counter at the timing at which its count of at least more than one horizontal synchronizing signal is reached.
Inventors
- 👤 Kunihiro Tsutsumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:50
CPC Classifications
G; G09; G09G; G09G1/00; G09G1/06; G09G1/14; G09G1/16; G09G5/00; G09G5/12; H; H04; H04N; H04N5/00; H04N5/222; H04N5/262; H04N5/278; H04N5/44; H04N5/445; H04N5/44504
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
198 words
An image display apparatus, comprising: a synchronizing signal separating circuit for generating vertical and horizontal synchronizing signals on receiving a composite image signal; a vertical address counter for starting to count said horizontal synchronizing signals on receiving the trailing edge of said vertical synchronizing signal at a reset input terminal thereof, wherein a vertical display position on a display is determined in accordance with the count given by said vertical address counter; and a first and a second D-type flip-flop and either a positive logical OR gate or a negative logical AND gate, said first D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and said vertical synchronizing signal at a data input terminal thereof, said second D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said first D-type flip-flop at a data input terminal thereof, wherein either gate receives said vertical synchronizing signal at first input terminal thereof and the negative logical output signal of said second D-type flip-flop at a second input terminal thereof to deliver the output of either gate to said reset input terminal of said vertical address counter.
Claim 2
Dependent Claim
198 words
An image display apparatus, comprising: a synchronizing signal separating circuit for generating vertical and horizontal synchronizing signals on receiving a composite image signal; a vertical address counter for starting to count said horizontal synchronizing signals on receiving the trailing edge of said vertical synchronizing signal at a reset input terminal thereof, wherein a vertical display position on a display is determined in accordance with the count given by said vertical address counter; and a first and a second D-type flip-flop and either a positive logical OR gate or a negative logical AND gate, said first D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and said vertical synchronizing signal at a data input terminal thereof, said second D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said first D-type flip-flop at a data input terminal thereof, wherein either gate receives said vertical synchronizing signal at first input terminal thereof and the negative logical output signal of said second D-type flip-flop at a second input terminal thereof to deliver the output of either gate to said reset input terminal of said vertical address counter.
Claim 3
Dependent Claim
234 words
An image display apparatus, comprising: a synchronizing signal separating circuit for generating vertical and horizontal synchronizing signals on receiving a composite image signal; a vertical address counter for starting to count said horizontal synchronizing signals on receiving the trailing edge of said vertical synchronizing signal at a reset input terminal thereof, wherein a vertical display position on a display is determined in accordance with the counter given by said vertical address counter; and a first, a second and a third D-type flip-flop and either a positive logical OR gate or a negative logical AND gate, wherein said first D-type flip-flop receives said horizontal synchronizing signal at a clock input terminal thereof and said vertical synchronizing signal at a data input terminal thereof, said second D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said first D-type flip-flop at a data input terminal thereof, said third D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said second D-type flip-flop at a data input terminal thereof, and either gate receiving said vertical synchronizing signal at a first input terminal thereof and the negative logical output signal of said third D-type flip-flop at a second input terminal thereof to deliver the output of either gate to said reset input terminal of said vertical address counter.
Claim 4
Dependent Claim
234 words
An image display apparatus, comprising: a synchronizing signal separating circuit for generating vertical and horizontal synchronizing signals on receiving a composite image signal; a vertical address counter for starting to count said horizontal synchronizing signals on receiving the trailing edge of said vertical synchronizing signal at a reset input terminal thereof, wherein a vertical display position on a display is determined in accordance with the counter given by said vertical address counter; and a first, a second and a third D-type flip-flop and either a positive logical OR gate or a negative logical AND gate, wherein said first D-type flip-flop receives said horizontal synchronizing signal at a clock input terminal thereof and said vertical synchronizing signal at a data input terminal thereof, said second D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said first D-type flip-flop at a data input terminal thereof, said third D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said second D-type flip-flop at a data input terminal thereof, and either gate receiving said vertical synchronizing signal at a first input terminal thereof and the negative logical output signal of said third D-type flip-flop at a second input terminal thereof to deliver the output of either gate to said reset input terminal of said vertical address counter.
References Cited (Backward Citations)
JPS6281175A
Cited
US4748504A
Cited
JPS62200876A
Cited
JPS6346076A
Cited
JPH0224574A
Cited
US4962428A
Cited
US5014128A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-25 | 2006-01-24 | 2006-07-26 | $7700.00 | Window Closed / Lapsed |