Image display apparatus

Claim 2

An image display apparatus, comprising: a synchronizing signal separating circuit for generating vertical and horizontal synchronizing signals on receiving a composite image signal; a vertical address counter for starting to count said horizontal synchronizing signals on receiving the trailing edge of said vertical synchronizing signal at a reset input terminal thereof, wherein a vertical display position on a display is determined in accordance with the count given by said vertical address counter; and a first and a second D-type flip-flop and either a positive logical OR gate or a negative logical AND gate, said first D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and said vertical synchronizing signal at a data input terminal thereof, said second D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said first D-type flip-flop at a data input terminal thereof, wherein either gate receives said vertical synchronizing signal at first input terminal thereof and the negative logical output signal of said second D-type flip-flop at a second input terminal thereof to deliver the output of either gate to said reset input terminal of said vertical address counter.

Claim 3

An image display apparatus, comprising: a synchronizing signal separating circuit for generating vertical and horizontal synchronizing signals on receiving a composite image signal; a vertical address counter for starting to count said horizontal synchronizing signals on receiving the trailing edge of said vertical synchronizing signal at a reset input terminal thereof, wherein a vertical display position on a display is determined in accordance with the counter given by said vertical address counter; and a first, a second and a third D-type flip-flop and either a positive logical OR gate or a negative logical AND gate, wherein said first D-type flip-flop receives said horizontal synchronizing signal at a clock input terminal thereof and said vertical synchronizing signal at a data input terminal thereof, said second D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said first D-type flip-flop at a data input terminal thereof, said third D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said second D-type flip-flop at a data input terminal thereof, and either gate receiving said vertical synchronizing signal at a first input terminal thereof and the negative logical output signal of said third D-type flip-flop at a second input terminal thereof to deliver the output of either gate to said reset input terminal of said vertical address counter.

Claim 4

An image display apparatus, comprising: a synchronizing signal separating circuit for generating vertical and horizontal synchronizing signals on receiving a composite image signal; a vertical address counter for starting to count said horizontal synchronizing signals on receiving the trailing edge of said vertical synchronizing signal at a reset input terminal thereof, wherein a vertical display position on a display is determined in accordance with the counter given by said vertical address counter; and a first, a second and a third D-type flip-flop and either a positive logical OR gate or a negative logical AND gate, wherein said first D-type flip-flop receives said horizontal synchronizing signal at a clock input terminal thereof and said vertical synchronizing signal at a data input terminal thereof, said second D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said first D-type flip-flop at a data input terminal thereof, said third D-type flip-flop receiving said horizontal synchronizing signal at a clock input terminal thereof and the positive logical output signal of said second D-type flip-flop at a data input terminal thereof, and either gate receiving said vertical synchronizing signal at a first input terminal thereof and the negative logical output signal of said third D-type flip-flop at a second input terminal thereof to deliver the output of either gate to said reset input terminal of said vertical address counter.