Patent US5336949A successfully refreshed from Google Patents.
US5336949A
Expired / Lapsed
US
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Logic circuit with enhancement type FET and Schottky gate
Assignee: Fujitsu Ltd
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Filing: 1992-08-05
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Granted: 1994-08-09
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Expires: 2012-08-05
Abstract
Abstract A logic circuit comprising an inverter which includes a load element connected at its one end to a high-potential power supply, an enhancement type N-channel field-effect transistor having a Schottky gate, the transistor being connected at its drain to another end of the load element and at its source to a low-potential power supply, an input terminal, and a gate-current control unit having negative resistance characteristic, the unit being provided between the input terminal and a gate of the enhancement type N-channel field-effect transistor for controlling a gate current that flows through the enhancement type N-channel field-effect transistor.
Inventors
- 👤 Takashi Mimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:18
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952; H10D84/0107; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/80; H10D84/811
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
159 words
A logic circuit having high and low potential power supply terminals, an input terminal and an output terminal and comprising: at least one inverter stage having an output node and comprising: a load element having a first end connected to the high potential power supply terminal and a second end connected to the output node, an enhancement type N-channel field-effect transistor having a Schottky gate, a drain connected to the output node, and thereby to the second end of the load element, and a source connected to the low-potential power supply terminal, gate-current control means, having a negative resistance characteristic, connecting the input terminal to the Schottky gate of the enhancement type N-channel field-effect transistor, for controlling the level of gate current flowing through the enhancement type N-channel field-effect transistor; and the input and output terminals of the logic circuit being connected respectively to the gate-current control means and the output node of the at least one inverter stage.
Claim 2
Dependent Claim
159 words
A logic circuit having high and low potential power supply terminals, an input terminal and an output terminal and comprising: at least one inverter stage having an output node and comprising: a load element having a first end connected to the high potential power supply terminal and a second end connected to the output node, an enhancement type N-channel field-effect transistor having a Schottky gate, a drain connected to the output node, and thereby to the second end of the load element, and a source connected to the low-potential power supply terminal, gate-current control means, having a negative resistance characteristic, connecting the input terminal to the Schottky gate of the enhancement type N-channel field-effect transistor, for controlling the level of gate current flowing through the enhancement type N-channel field-effect transistor; and the input and output terminals of the logic circuit being connected respectively to the gate-current control means and the output node of the at least one inverter stage.
Claim 3
Dependent Claim
76 words
A logic circuit as recited in claim 1, further comprising at least first and second said inverter stages, the input terminal of the logic circuit being connected to the gate-current control means of the first logic circuit, the output node of the first inverter stage being connected to the gate-current control means of the second inverter stage, and the output node of the second inverter stage being connected to the output terminal of the logic circuit.
Claim 4
Dependent Claim
18 words
A logic circuit as recited in claim 1, wherein the gate-current control means comprises a resonant tunneling diode.
Claim 5
Dependent Claim
17 words
A logic circuit as recited in claim 1, wherein the gate-current control means comprises an Esaki diode.
Claim 6
Dependent Claim
23 words
A logic circuit as recited in claim 1, wherein the load element comprises a depletion type N-channel field-effect transistor having a Schottky gate.
Claim 7
Dependent Claim
17 words
A logic circuit as recited in claim 1, wherein the load element comprises a resonant tunneling diode.
Claim 8
Dependent Claim
108 words
An integrated device comprising: a substrate; at least first and second semiconductor layers formed on the substrate and patterned to define electrically isolated first and second regions of the at least first and second layers; an enhancement type N-channel field-effect transistor formed in said first region of said first and second semiconductor layers on said substrate and having a Schottky gate and a drain; a resonant tunneling diode comprising plural additional semiconductor layers stacked on the second region of the at least first and second semiconductor layers, the resonant tunneling diode being connected to a selected one of the gate and the drain of the field effect transistor.
Claim 9
Dependent Claim
108 words
An integrated device comprising: a substrate; at least first and second semiconductor layers formed on the substrate and patterned to define electrically isolated first and second regions of the at least first and second layers; an enhancement type N-channel field-effect transistor formed in said first region of said first and second semiconductor layers on said substrate and having a Schottky gate and a drain; a resonant tunneling diode comprising plural additional semiconductor layers stacked on the second region of the at least first and second semiconductor layers, the resonant tunneling diode being connected to a selected one of the gate and the drain of the field effect transistor.
Claim 10
Dependent Claim
29 words
An integrated device as recited in claim 7, wherein the first and second regions are isolated by a doped channel extending between and surrounding the first and second regions.
Claim 11
Dependent Claim
42 words
An integrated device as recited in claim 7, wherein, in the first region, the first and second semiconductor layers define an interface therebetween, the first layer defining a channel layer of the field effect transistor at the interface with the second layer.
Claim 12
Dependent Claim
23 words
An integrated device as recited in claim 7, wherein the resonant tunneling diode is connected to the gate of the field effect transistor.
Claim 13
Dependent Claim
23 words
An integrated device as recited in claim 7, wherein the resonant tunneling diode is connected to the drain of the field effect transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |