Patent US5339399A successfully refreshed from Google Patents.
US5339399A
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Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus
Assignee: Intel Corp
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Filing: 1991-04-12
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Granted: 1994-08-16
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Expires: 2011-04-12
Abstract
Abstract A cache controller sits in parallel with a microprocessor bus and includes a tag RAM for associatively searching a directory for cache data-array addresses. Two normal address latches are provided to capture a cycle address in case the current cycle is extended by a pending tag RAM access. At any time, except when the next cycle has started, but during which the current cycle is in progress, one latch is open to an input buffer such that the input address is latched by that latch. The other latch holds the current cycle address until the cycle ends. The current cycle can be extended with snoops. The current cycle address has to be maintained as long as the cycle is still in progress. In the meantime, the external cycle might have ended and a next cycle started. The second address latch is used to capture the address corresponding to this new cycle. As signal selects which of the two latches will supply the address via a MUX to the tag RAM. Logic switches the two input address latches so that the tag RAM sees a constant address for the duration of a cycle while at the same time a new cycle address can be received.
Inventors
- 👤 Yong Lee
- 👤 Nagraj Palasamudram
- 👤 James Nadir
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:40
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
263 words
In a data processing system including an input address bus; a cache controller connected to said input address bus; a cache data-array connected to said cache controller and to said input address bus; said input address bus carrying a bus address; control logic in said cache controller for controlling references to said cache data-array comprising: a first address latch connected to said input address bus; a second address latch connected to said input address bus; clocking means for generating a first clock signal and a second clock signal; first means connected to said clocking means, responsive to said first clock signal for capturing a current address on said input address bus into one of said first and second address latches at the beginning of a current cycle; second means connected to said clocking means, responsive to said second clock signal for capturing a next address on said input address bus into the other one of said first and second address latches at the beginning of a next cycle; said other one of said latches holding said next address until said current cycle ends; third means connected to said first and second latches and to said clocking means for alternately selecting one of said first and second latches on successive cycles of said clocking means to thereby receive an input address at each successive clock cycle; and, fourth means connected to an output of said first address latch and to an output of said second address latch for gating of one of either said current address or said next address to said control logic.
Claim 2
Dependent Claim
263 words
In a data processing system including an input address bus; a cache controller connected to said input address bus; a cache data-array connected to said cache controller and to said input address bus; said input address bus carrying a bus address; control logic in said cache controller for controlling references to said cache data-array comprising: a first address latch connected to said input address bus; a second address latch connected to said input address bus; clocking means for generating a first clock signal and a second clock signal; first means connected to said clocking means, responsive to said first clock signal for capturing a current address on said input address bus into one of said first and second address latches at the beginning of a current cycle; second means connected to said clocking means, responsive to said second clock signal for capturing a next address on said input address bus into the other one of said first and second address latches at the beginning of a next cycle; said other one of said latches holding said next address until said current cycle ends; third means connected to said first and second latches and to said clocking means for alternately selecting one of said first and second latches on successive cycles of said clocking means to thereby receive an input address at each successive clock cycle; and, fourth means connected to an output of said first address latch and to an output of said second address latch for gating of one of either said current address or said next address to said control logic.
Claim 3
Dependent Claim
107 words
The combination in accordance with claim 1 further comprising: a snoop cycle signal line for signaling that a snoop address is on said address bus; a first snoop latch connected to said input address bus and responsive to said snoop cycle signal line for storing said snoop address; and, a second snoop latch connected to said first snoop latch; said clocking means including a third clock signal for transferring said snoop address in said first snoop latch to said second snoop latch; said fourth means further including fifth means for gating one of said current address, said next address, or said snoop address to said control logic.
Claim 4
Dependent Claim
170 words
In a data processing system including an input address bus; a cache controller connected to said input address bus; a cache data-array connected to said cache controller and to said input address bus; control logic in said cache controller for controlling references to said cache data-array including a first address latch, and a second address latch, the method comprising the steps of: A. capturing a current address on said input address bus into one of said first or second address latches at the beginning of a current cycle; B. capturing a next address on said input address bus into the other one of said first and second address latches at the beginning of a next cycle; C. holding said current address until said current cycle ends; D. alternately selecting one of said first and second latches on successive cycles of said clocking means to receive an input address at the successive clock cycles; and, E. gating one of either said current address or said next address to said control logic.
Claim 5
Dependent Claim
170 words
In a data processing system including an input address bus; a cache controller connected to said input address bus; a cache data-array connected to said cache controller and to said input address bus; control logic in said cache controller for controlling references to said cache data-array including a first address latch, and a second address latch, the method comprising the steps of: A. capturing a current address on said input address bus into one of said first or second address latches at the beginning of a current cycle; B. capturing a next address on said input address bus into the other one of said first and second address latches at the beginning of a next cycle; C. holding said current address until said current cycle ends; D. alternately selecting one of said first and second latches on successive cycles of said clocking means to receive an input address at the successive clock cycles; and, E. gating one of either said current address or said next address to said control logic.
Claim 6
Dependent Claim
87 words
The method in accordance with claim 3 further comprising the steps of: F. signaling that a snoop address is on said address bus; G. storing said snoop address in a first snoop latch connected to said address bus in response to a first clock signal; H. storing said snoop address in a second snoop latch connected to said first snoop latch in response to a second clock signal; I. gating one of either said current address, said next address or said snoop address to said control logic.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-15 | 1998-02-14 | 1998-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-15 | 2002-02-14 | 2002-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-15 | 2006-02-14 | 2006-08-16 | $7700.00 | Window Closed / Lapsed |