Semiconductor memory device having electrically isolated memory and logic sections

Claim 2

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a high-resistance element constituting a memory cell; a low-resistance line connected to said high-resistance element; a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching element arranged between said low-resistance line and said power source line, and which is controlled by said control signal from said control circuit, thereby electrically separating said memory section and said logic section from each other.

Claim 3

A device according to claim 1, wherein said switching element is a MOS transistor having a low 0N resistance.

Claim 4

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a memory cell array obtained by arranging memory cells having high-resistance elements in an array form; a plurality of word lines and a plurality of bit line pairs for decoding said memory cells of said memory cell arrays; a plurality of low-resistance lines arranged in correspondence with and along said word lines so as to be perpendicular to said bit line pairs, said low-resistance lines serving as power source lines of said memory cells and being connected to the high-resistance elements; a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching circuit constituted by a plurality of switching elements arranged between said low-resistance lines and said power source lines, said switching elements being controlled by said control signal, thereby electrically separating said memory section and said logic section from each other.

Claim 5

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a memory cell array obtained by arranging memory cells having high-resistance elements in an array form; a plurality of word lines and a plurality of bit line pairs for decoding said memory cells of said memory cell arrays; a plurality of low-resistance lines arranged in correspondence with and along said word lines so as to be perpendicular to said bit line pairs, said low-resistance lines serving as power source lines of said memory cells and being connected to the high-resistance elements; a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching circuit constituted by a plurality of switching elements arranged between said low-resistance lines and said power source lines, said switching elements being controlled by said control signal, thereby electrically separating said memory section and said logic section from each other.

Claim 6

A device according to claim 1, wherein said switching elements are MOS transistors each having a low ON resistance.

Claim 7

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a memory cell array obtained by arranging memory cells having high-resistance elements in an array form; a plurality of word lines and a plurality of bit line pairs perpendicular thereto, said word lines serving as power source lines of said memory cells and being connected to the high-resistance elements a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching circuit constituted by a plurality of switching elements arranged between said low-resistance lines and said power source lines, said switching elements being controlled by said control signal, thereby electrically separating said memory section and said logic section from each other.

Claim 8

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a memory cell array obtained by arranging memory cells having high-resistance elements in an array form; a plurality of word lines and a plurality of bit line pairs perpendicular thereto, said word lines serving as power source lines of said memory cells and being connected to the high-resistance elements a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching circuit constituted by a plurality of switching elements arranged between said low-resistance lines and said power source lines, said switching elements being controlled by said control signal, thereby electrically separating said memory section and said logic section from each other.

Claim 9

A device according to claim 1, wherein said switching elements are MOS transistors each having a low ON resistance.

Claim 10

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a high-resistance element constituting a memory cell; a low-resistance line connected to said high-resistance element; a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching element arranged between said low-resistance line and said power source line, and which is controlled by said control signal from said control circuit, thereby said switching element is completely turned off.

Claim 11

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a high-resistance element constituting a memory cell; a low-resistance line connected to said high-resistance element; a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching element arranged between said low-resistance line and said power source line, and which is controlled by said control signal from said control circuit, thereby said switching element is completely turned off.

Claim 12

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a memory cell array obtained by arranging memory cells having high-resistance elements in an array form; a plurality of word lines and a plurality of bit line pairs for decoding said memory cells of said memory cell arrays; a plurality of low-resistance lines arranged in correspondence with and along said word lines so as to be perpendicular to said bit line pairs, said low-resistance lines serving as power source lines of said memory cells and being connected to the high-resistance elements; a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching circuit constituted by a plurality of switching elements arranged between said low-resistance lines and said power source lines, said switching elements being controlled by said control signal, thereby said switching circuit is completely turned off.

Claim 13

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a memory cell array obtained by arranging memory cells having high-resistance elements in an array form; a plurality of word lines and a plurality of bit line pairs for decoding said memory cells of said memory cell arrays; a plurality of low-resistance lines arranged in correspondence with and along said word lines so as to be perpendicular to said bit line pairs, said low-resistance lines serving as power source lines of said memory cells and being connected to the high-resistance elements; a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching circuit constituted by a plurality of switching elements arranged between said low-resistance lines and said power source lines, said switching elements being controlled by said control signal, thereby said switching circuit is completely turned off.

Claim 14

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a memory cell array obtained by arranging memory cells having high-resistance elements in an array form; a plurality of word lines and a plurality of bit line pairs perpendicular thereto, said word line serving as power source lines of said memory cells and being connected to the high-resistance elements; a plurality of low-resistance lines which are arranged in parallel to said bit line pairs and vertically to said word lines, which serve as power source lines of said memory cells, and which are connected to the high-resistance elements; a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching circuit constituted by a plurality of switching elements arranged between said low-resistance lines and said power source lines, said switching elements being controlled by said control signal, thereby said switching circuit is completely turned off.

Claim 15

A semiconductor device in which a memory section and a logic section are formed on the same semiconductor chip, comprising: a memory cell array obtained by arranging memory cells having high-resistance elements in an array form; a plurality of word lines and a plurality of bit line pairs perpendicular thereto, said word line serving as power source lines of said memory cells and being connected to the high-resistance elements; a plurality of low-resistance lines which are arranged in parallel to said bit line pairs and vertically to said word lines, which serve as power source lines of said memory cells, and which are connected to the high-resistance elements; a power source line serving as a power source path from a power source pad; a control circuit for outputting a control signal; and a switching circuit constituted by a plurality of switching elements arranged between said low-resistance lines and said power source lines, said switching elements being controlled by said control signal, thereby said switching circuit is completely turned off.