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US5361235A
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Method for erasing data stored in a non-volatile semiconductor memory by using a predetermined series of pulses
Assignee: NEC Electronics Corp
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Filing: 1992-04-09
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Granted: 1994-11-01
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Expires: 2012-04-09
Abstract
Abstract A method for erasing data stored in a non-volatile semiconductor memory is applied to a memory cell transistor including a p-type well region, a source and a drain formed within the p-type well region, and a composite gate including a floating gate electrode formed on the p-type well region. In the method, a plurality of pulses having a high positive voltage is applied to the p-type well region so that a product (I×N) of a pulse interval (I) and a number of the plurality of pulses (N) becomes not smaller than 0.1 s on condition that the control gate electrode is fixed to the ground level and the source and drain are kept at a floating state.
Inventors
- 👤 Noriaki Kodama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:32
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
139 words
A method for erasing data stored in a non-volatile semiconductor memory, comprising the steps of: providing a memory cell transistor comprising a p-type well region, a source and a drain formed within said p-type well region, a composite gate consisting of a first gate insulation layer, a floating gate electrode, a second grate insulation layer and a control gate electrode formed on said p-type well region; and applying a predetermined number (N) of serial pulses each having a high positive voltage and a pulse interval (I) relative to an adjacent pulse, to said p-type well region when said control gate electrode is fixed to the ground level and said source and drain are kept at a floating state, the product (I×N) being not smaller than a predetermined time, wherein said pulse interval (I) is not smaller than 1 ms.
Claim 2
Independent Claim
139 words
A method for erasing data stored in a non-volatile semiconductor memory, comprising the steps of: providing a memory cell transistor comprising a p-type well region, a source and a drain formed within said p-type well region, a composite gate consisting of a first gate insulation layer, a floating gate electrode, a second grate insulation layer and a control gate electrode formed on said p-type well region; and applying a predetermined number (N) of serial pulses each having a high positive voltage and a pulse interval (I) relative to an adjacent pulse, to said p-type well region when said control gate electrode is fixed to the ground level and said source and drain are kept at a floating state, the product (I×N) being not smaller than a predetermined time, wherein said pulse interval (I) is not smaller than 1 ms.
Claim 3
Dependent Claim
46 words
A method for erasing data stored in a non-volatile semiconductor memory, according to claim 1, wherein: said p-type well region is formed within an n-type semiconductor substrate; and said series of pulses is applied to said n-type semiconductor substrate as well as said p-type well region.
Claim 4
Dependent Claim
46 words
A method for erasing data stored in a non-volatile semiconductor memory, according to claim 1, wherein: said p-type well region is formed within an n-type well region; and said series of pulses is applied to said n-type well region as well as said p-type well region.
Claim 5
Dependent Claim
38 words
A method for erasing data stored in a non-volatile semiconductor memory, according to claim 3, wherein: said n-type well region is formed within a p-type semiconductor substrate; and said p-type semiconductor substrate is fixed to the ground level.
Claim 6
Dependent Claim
38 words
A method for erasing data stored in a non-volatile semiconductor memory, according to claim 1, wherein: said series of pulses are applied to said p-type well region so that said product (I×N) becomes not smaller than 0.1 s.
Claim 7
Dependent Claim
29 words
A method for erasing data stored in a non-volatile semiconductor memory, according to claim 1, wherein: said number of said series of pulses (N) is not smaller than ten.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |